Patents by Inventor Katsumi Tsuneno
Katsumi Tsuneno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10958250Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.Type: GrantFiled: June 8, 2018Date of Patent: March 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Chiemi Hashimoto, Kosuke Yayama, Katsumi Tsuneno, Tomokazu Matsuzaki
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Patent number: 10496782Abstract: According to an embodiment, element models include a first transistor model, a second transistor model, and a variable resistor model. The first transistor model simulates a characteristic of a selection gate transistor whose channel resistance is changed by a selection gate voltage applied to a selection gate. The second transistor model simulates a characteristic of a memory gate transistor whose channel resistance is changed by a memory gate voltage applied to a memory gate. The variable resistor model has a resistance value which is changed in accordance with the selection gate voltage and the memory gate voltage and which is set to correspond to a gap region formed in a lower part of an insulating film insulating between the selection gate and the memory gate. The variable resistor model is provided between the first transistor model and the second transistor model.Type: GrantFiled: December 5, 2017Date of Patent: December 3, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Risho Koh, Mitsuru Miyamori, Katsumi Tsuneno
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Patent number: 10446655Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: GrantFiled: October 24, 2018Date of Patent: October 15, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu
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Publication number: 20190067428Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: ApplicationFiled: October 24, 2018Publication date: February 28, 2019Applicant: Renesas Electronics CorporationInventors: Tetsuya WATANABE, Mitsuru MIYAMORI, Katsumi TSUNENO, Takashi SHIMIZU
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Publication number: 20180375497Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.Type: ApplicationFiled: June 8, 2018Publication date: December 27, 2018Inventors: Chiemi HASHIMOTO, Kosuke YAYAMA, Katsumi TSUNENO, Tomokazu MATSUZAKI
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Patent number: 10164036Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: GrantFiled: October 27, 2017Date of Patent: December 25, 2018Assignee: Renesas Electronics CorporationInventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu
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Patent number: 10134857Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: GrantFiled: October 27, 2017Date of Patent: November 20, 2018Assignee: Renesas Electronics CorporationInventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu
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Publication number: 20180181696Abstract: According to an embodiment, element models include a first transistor model, a second transistor model, and a variable resistor model. The first transistor model simulates a characteristic of a selection gate transistor whose channel resistance is changed by a selection gate voltage applied to a selection gate. The second transistor model simulates a characteristic of a memory gate transistor whose channel resistance is changed by a memory gate voltage applied to a memory gate. The variable resistor model has a resistance value which is changed in accordance with the selection gate voltage and the memory gate voltage and which is set to correspond to a gap region formed in a lower part of an insulating film insulating between the selection gate and the memory gate. The variable resistor model is provided between the first transistor model and the second transistor model.Type: ApplicationFiled: December 5, 2017Publication date: June 28, 2018Inventors: Risho Koh, Mitsuru Miyamori, Katsumi Tsuneno
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Publication number: 20180047820Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: ApplicationFiled: October 27, 2017Publication date: February 15, 2018Applicant: Renesas Electronics CorporationInventors: Tetsuya WATANABE, Mitsuru MIYAMORI, Katsumi TSUNENO, Takashi SHIMIZU
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Patent number: 9837501Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: GrantFiled: February 14, 2017Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu
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Publication number: 20170154969Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: ApplicationFiled: February 14, 2017Publication date: June 1, 2017Applicant: Renesas Electronics CorporationInventors: Tetsuya WATANABE, Mitsuru MIYAMORI, Katsumi TSUNENO, Takashi SHIMIZU
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Patent number: 9620602Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: GrantFiled: August 10, 2015Date of Patent: April 11, 2017Assignee: Renesas Electronics CorporationInventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu
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Publication number: 20160056154Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.Type: ApplicationFiled: August 10, 2015Publication date: February 25, 2016Applicant: Renesas Electronics CorporationInventors: Tetsuya WATANABE, Mitsuru MIYAMORI, Katsumi TSUNENO, Takashi SHIMIZU
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Patent number: 6063686Abstract: A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer.Type: GrantFiled: February 13, 1998Date of Patent: May 16, 2000Inventors: Hiroo Masuda, Hisako Sato, Takahide Nakamura, Katsumi Tsuneno, Kimiko Aoyama, Takahide Ikeda, Nobuyoshi Natsuaki, Shinichiro Mitani