Abstract: A micro-computer system using a DRAM can refresh the DRAM in a certain interval cycle to maintain the memory contents or refresh the DRAM memory even when the system is set into the standby mode and the clock generator has stopped providing clock timing signals to the memory refreshing circuit. Accordingly, the DRAM memory is refreshed by automatically changing from the interval refresh mode to the self refresh mode when the system operation changes from the normal operation to the standby operation, thus achieving low system power consumption.

Abstract: A security circuit for protecting data stored in an internal memory of a microcomputer has a first memory for storing an externally applied security code and a latch circuit for latching a key code in order to read data stored in the internal memory. A comparator determines whether or not the security code in the first memory and the key code in the latch circuit are in agreement and outputs comparison results for storage in a second memory. A read control circuit uses the comparison results stored in the second memory as the basis for prohibiting reading of data in the internal memory when the security code and the key code are not in agreement, and for using an externally applied output control signal as the basis to control reading of data stored in the internal memory when there is agreement.