Patents by Inventor Katsumi Yoneda

Katsumi Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7084077
    Abstract: A method for fabricating a high density semiconductor integrated circuit device with a multilayer interconnect wiring structure is disclosed. This structure has a low-dielectric constant insulator film including an organic thin-film with its dielectric constant ranging from about 2.0 to about 2.4. To fabricate the multilayer wiring structure, a substrate with an inorganic film for use as an underlayer dielectric film is prepared. Then, apply plasma processing, such as plasma-assisted chemical vapor-phase growth, to a top surface of the inorganic underlayer dielectric film in environment that contains therein organic silane-based chemical compounds, thereby to form on the inorganic film surface a hydrophobic surface layer with a contact angle with water being 50° or higher. Next, form on the plasma-processed hydrophobic surface an organic film including a fluorinated aromatic carbon hydride polymer film.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: August 1, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naruhiko Kaji, Katsumi Yoneda
  • Patent number: 7056825
    Abstract: In a method for manufacturing a semiconductor device having a multi-layer insulating film, a first insulating film is formed as one layer of the multi-layer insulating film, and a plasma treatment is performed on the surface of the first insulating film in an ambient of helium and argon, containing 5 to 31% Ar. After the plasma treatment, a second insulating film, different from the first insulating film, is formed on the first insulating film as another layer of the multi-layer insulating film.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 6, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Katsumi Yoneda, Toru Yoshie
  • Publication number: 20050085097
    Abstract: A method for fabricating a high density semiconductor integrated circuit device with a multilayer interconnect wiring structure is disclosed. This structure has a low-dielectric constant insulator film including an organic thin-film with its dielectric constant ranging from about 2.0 to about 2.4. To fabricate the multilayer wiring structure, a substrate with an inorganic film for use as an underlayer dielectric film is prepared. Then, apply plasma processing, such as plasma-assisted chemical vapor-phase growth, to a top surface of the inorganic underlayer dielectric film in environment that contains therein organic silane-based chemical compounds, thereby to form on the inorganic film surface a hydrophobic surface layer with a contact angle with water being 50° or higher. Next, form on the plasma-processed hydrophobic surface an organic film including a fluorinated aromatic carbon hydride polymer film.
    Type: Application
    Filed: August 27, 2004
    Publication date: April 21, 2005
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Naruhiko Kaji, Katsumi Yoneda
  • Publication number: 20040248395
    Abstract: In a method for manufacturing a semiconductor device having a multi-layer insulating film, a first insulating film is formed as one layer of the multi-layer insulating film, and a plasma treatment is performed on the surface of the first insulating film in an ambient of helium and argon, containing 5 to 31% Ar. After the plasma treatment, a second insulating film, different from the first insulating film, is formed on the first insulating film as another layer of the multi-layer insulating film.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 9, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Katsumi Yoneda, Toru Yoshie
  • Patent number: 5855682
    Abstract: A plasma thin-film forming apparatus comprises a vacuum vessel, a positive and a negative electrode disposed in the vacuum vessel so that the discharge surfaces may face each other at a required interval, an exhaust means for making a required vacuum condition in the interior of the vacuum vessel, a high-voltage impressing means for generating DC glow discharge by impressing high voltage between the positive and the negative electrode, and a gas-inducting means for supplying metal compound-including gas into the vacuum vessel. The gas-inducting means comprises a flexible holding member gastightly fitted to a sublimation chamber communicating with the vacuum vessel and having a hollow portion therein and a glass container inserted in the hollow portion of the holding member and enclosing a predetermined quantity of crysterized osmium tetraoxide therein. The exhaust means is provided with a material gas-adsorbing means in the exhaust port.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: January 5, 1999
    Assignee: Nippon Laser & Electronics Lab
    Inventor: Katsumi Yoneda