Patents by Inventor Katsunobu Fushikida

Katsunobu Fushikida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4549305
    Abstract: The present invention features an ADPCM decoder of the instantaneous companding type which comprises two memory circuits (each preferably PROM). The first memory contains a plurality of differential values and the second a plurality of step size control codes. The memories receives ADPCM input codes which function as address signals. The memories are connected through an adder and a shift register feedback connected with the adder. The first memory receives two inputs, one of which is an ADPCM input code and the other is an input consisting of the sum of the current output of the second memory plus the previous value outputted thereby. The first memory produces a differential value on the basis of the two inputs applied.
    Type: Grant
    Filed: May 11, 1983
    Date of Patent: October 22, 1985
    Assignee: NEC Corporation
    Inventor: Katsunobu Fushikida
  • Patent number: 4486899
    Abstract: There is disclosed a system for the extraction of pole parameter values. The system comprises an autocorrelation value calculating circuit receiving an input voice signal through a time window, for calculating an autocorrelation value V.sub.i (i=0, 1, 2, . . .) of the input voice signal within the time window; a linear prediction coefficient memory circuit for storing linear prediction coefficients (.alpha..sub.1, .alpha..sub.2) corresponding to various pole parameter values; a signal processor for receiving as its input the output value V.sub.i of the autocorrelation value calculating circuit, performing thereon an arithmetic operation according to the following formula using the prediction coefficients (.alpha..sub.1, .alpha..sub.2) supplied by the linear prediction coefficient memory circuit:r.sub.i =(l+.alpha..sub.1.sup.2 +.alpha..sub.2.sup.2)V.sub.i -(.alpha..sub.1 -.alpha..sub.1 .alpha..sub.2)V.sub.i+1 -(.alpha..sub.1 -.alpha..sub.1 .alpha..sub.2)V.sub.i-1 -.alpha..sub.2 V.sub.i-2 -.alpha..sub.2 V.sub.
    Type: Grant
    Filed: March 16, 1982
    Date of Patent: December 4, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Katsunobu Fushikida