Patents by Inventor Katsunobu Mori
Katsunobu Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100294342Abstract: A solar cell module 1 includes a plurality of solar cells 30. Each of the plurality of solar cells 30 is disposed on a corresponding one of a plurality of pad sections in such a manner that the each of the plurality of solar cells 30 is electrically connected to the corresponding one of the plurality of pad sections. The each of the plurality of solar cells 30 is electrically connected to a corresponding inner lead section 120. A cathode section 114 and an anode section 116 feed an electric current generated by the plurality of solar cells 30. A metal lead frame is provided such that the plurality of pad sections, the inner lead sections 120, the cathode section 114 and the anode section 116 are provided therein as a part of the lead frame itself. This configuration enables the solar cell module 1 to endure against bending stress and to be curved. As a result, it is possible to provide a solar cell module which can be disposed along a curved surface of an electronics device.Type: ApplicationFiled: May 20, 2010Publication date: November 25, 2010Inventors: Hiroyuki Nakanishi, Kohji Miyata, Yoshihide Iwazaki, Seiji Ishihara, Masato Yokobayashi, Etsuko Ishizuka, Kiyoharu Shimano, Katsunobu Mori
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Patent number: 7445958Abstract: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.Type: GrantFiled: June 26, 2006Date of Patent: November 4, 2008Assignee: Sharp Kabushiki KaishaInventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Publication number: 20060237848Abstract: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.Type: ApplicationFiled: June 26, 2006Publication date: October 26, 2006Inventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Patent number: 7091616Abstract: A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.Type: GrantFiled: June 7, 2002Date of Patent: August 15, 2006Assignee: Sharp Kabushiki KaishaInventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Publication number: 20060163728Abstract: A semiconductor device includes: a semiconductor chip having a plurality of electrode pads formed on a principal surface thereof; a sealing resin, which covers both (i) side surfaces of the semiconductor chip and (ii) a surface of the semiconductor chip opposite to the principal surface; and external connection pads, which are provided on both (I) the principal surface and (II) a surface of the sealing resin flush with the principal surface, and which are electrically connected to the electrode pads. Thus, a semiconductor device is provided which makes it possible to place external connection pads at wider intervals, and which makes it possible to widen wires and to place the wires at wider intervals.Type: ApplicationFiled: January 19, 2006Publication date: July 27, 2006Applicant: SHARP KABUSHIKI KAISHAInventors: Hiroyuki Nakanishi, Katsunobu Mori
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Publication number: 20050194686Abstract: A semiconductor device according to the present invention comprises an electrode pad electrically conducted to an electric circuit formed on an element-formed surface of a silicon wafer; a wiring pattern re-wired by being electrically conducted to the electrode pad; and an oxide film formed on a surface of the wiring pattern, the oxide film being formed by subjecting the wiring pattern to oxidization. With the provision of oxide film, the semiconductor device prevents a decrease in reliability in terms of electric characteristic or the like, and also achieves reduction in fabrication cost compared to a conventional semiconductor device.Type: ApplicationFiled: March 7, 2005Publication date: September 8, 2005Applicant: SHARP KABUSHIKI KAISHAInventors: Yoshihide Iwazaki, Shinji Suminoe, Katsunobu Mori
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Patent number: 6940175Abstract: A semiconductor device includes (i) spacers between a first electronic component and a second electronic component facing each other, for keeping a distance between the first and second electronic components constant and (ii) combining parts for combining the first electronic component with the second electronic component. The spacers are made of liquid resin material made of thermosetting resin, and the combining parts are made of liquid conductive combining material including metal and thermosetting resin.Type: GrantFiled: June 7, 2002Date of Patent: September 6, 2005Assignee: Sharp Kabushiki KaishaInventors: Yoshihide Iwazaki, Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori
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Patent number: 6921980Abstract: An integrated semiconductor circuit includes a semiconductor chip on which surface a plurality of connection electrodes are formed, a lower insulating layer covering the surface of the semiconductor chip such that the connection electrodes are exposed, a plurality of wiring portions formed on the lower insulating layer, each of the wiring portions being connected to the connection electrode at one end and provided with a component connection portion at the other end, an upper insulating layer covering the wiring portions such that the component connection portions are exposed, and an electronic component connected between different component connection portions.Type: GrantFiled: January 31, 2002Date of Patent: July 26, 2005Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Nakanishi, Toshiya Ishio, Katsunobu Mori
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Publication number: 20050104165Abstract: A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.Type: ApplicationFiled: December 29, 2004Publication date: May 19, 2005Applicant: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori, Yoshihide Iwazaki, Shinji Suminoe
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Patent number: 6838748Abstract: A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.Type: GrantFiled: May 9, 2003Date of Patent: January 4, 2005Assignee: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori, Yoshihide Iwazaki, Shinji Suminoe
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Patent number: 6831002Abstract: A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.Type: GrantFiled: September 13, 2002Date of Patent: December 14, 2004Assignee: Sharp Kabushiki KaishaInventors: Yoshihide Iwazaki, Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Takamasa Tanaka, Katsunobu Mori
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Patent number: 6784528Abstract: In order to simplify a providing method of a wiring that electrically connects a semiconductor integrated circuit to a substrate, the semiconductor integrated circuit that is covered with an insulating layer except for an electrode area having an electrode pad is fixed on a formation side of the substrate having a terminal connected to the semiconductor integrated circuit so that the electrode pad is exposed. Next, a metallic thin film is provided on a wiring area on which a wiring for electrically connecting the electrode pad to the terminal is provided. Further, the wiring is provided on the metallic film of the wiring area in accordance with plating.Type: GrantFiled: October 11, 2002Date of Patent: August 31, 2004Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Nakanishi, Toshiya Ishio, Katsunobu Mori
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Publication number: 20030218257Abstract: A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.Type: ApplicationFiled: May 9, 2003Publication date: November 27, 2003Inventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori, Yoshihide Iwazaki, Shinji Suminoe
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Publication number: 20030134509Abstract: A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.Type: ApplicationFiled: September 13, 2002Publication date: July 17, 2003Inventors: Yoshihide Iwazaki, Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Takamasa Tanaka, Katsunobu Mori
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Publication number: 20030111721Abstract: In order to simplify a providing method of a wiring that electrically connects a semiconductor integrated circuit to a substrate, the semiconductor integrated circuit that is covered with an insulating layer except for an electrode area having an electrode pad is fixed on a formation side of the substrate having a terminal connected to the semiconductor integrated circuit so that the electrode pad is exposed. Next, a metallic thin film is provided on a wiring area on which a wiring for electrically connecting the electrode pad to the terminal is provided. Further, the wiring is provided on the metallic film of the wiring area in accordance with plating.Type: ApplicationFiled: October 11, 2002Publication date: June 19, 2003Inventors: Hiroyuki Nakanishi, Toshiya Ishio, Katsunobu Mori
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Patent number: 6552426Abstract: The present invention provides a quality and reliable high-density package (Chip Size Package) semiconductor device without problems related to the manufacturing process. The semiconductor device includes the first semiconductor substrate piece having electrode pads formed on its principle surface, and a second semiconductor mounting piece mounted thereon via a first insulating film and a die-attaching material. On the surface opposite the first semiconductor substrate piece of the second semiconductor substrate piece, formed are wiring patterns and a second insulating film for protecting the wiring patterns. The wiring patterns include electrode pads, wires, and lands where external connection terminals are provided.Type: GrantFiled: May 3, 2001Date of Patent: April 22, 2003Assignee: Sharp Kabushiki KaishaInventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori
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Publication number: 20030025173Abstract: A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.Type: ApplicationFiled: June 7, 2002Publication date: February 6, 2003Inventors: Shinji Suminoe, Hiroyuki Nakanishi, Toshiya Ishio, Yoshihide Iwazaki, Katsunobu Mori
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Publication number: 20020190392Abstract: A semiconductor device includes (i) spacers between a first electronic component and a second electronic component facing each other, for keeping a distance between the first and second electronic components constant and (ii) combining parts for combining the first electronic component with the second electronic component. The spacers are made of liquid resin material made of thermosetting resin, and the combining parts are made of liquid conductive combining material including metal and thermosetting resin.Type: ApplicationFiled: June 7, 2002Publication date: December 19, 2002Inventors: Yoshihide Iwazaki, Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori
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Publication number: 20020113323Abstract: An integrated semiconductor circuit includes a semiconductor chip on which surface a plurality of connection electrodes are formed, a lower insulating layer covering the surface of the semiconductor chip such that the connection electrodes are exposed, a plurality of wiring portions formed on the lower insulating layer, each of the wiring portions being connected to the connection electrode at one end and provided with a component connection portion at the other end, an upper insulating layer covering the wiring portions such that the component connection portions are exposed, and an electronic component connected between different component connection portions.Type: ApplicationFiled: January 31, 2002Publication date: August 22, 2002Inventors: Hiroyuki Nakanishi, Toshiya Ishio, Katsunobu Mori
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Patent number: 6396157Abstract: A semiconductor integrated circuit device in accordance with the present invention is provided with first electrode pads, a first insulation layer and a second insulation layer. The first electrode pad are formed on the circuit formation face side of an IC chip. The first insulation layer is placed on areas other than the upper portions of the first electrode pads. The second insulation layer, which is made from a photosensitive material, is formed on the first insulation layer with an opening section for allowing at least one portion of the first electrode, the wire and at least one portion of the second electrode to be exposed. Here, the wire and the second electrode are formed by filling the opening section of the second insulation layer with particles of a conductive material.Type: GrantFiled: January 3, 2001Date of Patent: May 28, 2002Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Nakanishi, Katsunobu Mori, Toshiya Ishio, Shinji Suminoe