Patents by Inventor Katsunobu Noguchi

Katsunobu Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of refreshing the same
    Patent number: 8451677
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: May 28, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Katsunobu Noguchi
  • SEMICONDUCTOR DEVICE FOR PERFORMING A REFRESH OPERATION
    Publication number: 20120307583
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 6, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tetsuaki OKAHIRO, Hiromasa NODA, Katsunobu NOGUCHI
  • Semiconductor device for performing a refresh operation
    Patent number: 8274855
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: September 25, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Katsunobu Noguchi
  • Semiconductor device and method of refreshing the same
    Patent number: 8068375
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: November 29, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Katsunobu Noguchi
  • SEMICONDUCTOR DEVICE AND METHOD OF REFRESHING THE SAME
    Publication number: 20110273948
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Application
    Filed: June 24, 2011
    Publication date: November 10, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tetsuaki OKAHIRO, Hiromasa NODA, Katsunobu NOGUCHI
  • SEMICONDUCTOR DEVICE AND METHOD OF REFRESHING THE SAME
    Publication number: 20100128548
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Application
    Filed: January 14, 2009
    Publication date: May 27, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Katsunobu Noguchi