Patents by Inventor Katsunobu Suzuki
Katsunobu Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210165183Abstract: An actuator includes: a movable unit to hold an object to be driven; a fixed unit to support the movable unit thereon to make the movable unit rotatable; and a structure for supporting the movable unit with respect to the fixed unit. The structure includes: a sphere; and a pair of holding members to clamp the sphere between themselves. A space is left to let the sphere roll while shifting a center position thereof with respect to at least one of the pair of holding members.Type: ApplicationFiled: September 21, 2018Publication date: June 3, 2021Inventors: Yasuaki KAMEYAMA, Hironori TOMITA, Masahiro INATA, Katsunobu SUZUKI
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Patent number: 7888808Abstract: A system in package integrating a plurality of semiconductor chips, including a first chip mounted commonly in a plurality of system in packages and at least including a CPU, a second chip having a different specification for each of the plurality of system in packages depending on a connection of internal lines, and a module substrate including the first chip and the second chip adjacent to each other and having a shape common to the plurality of system in packages. The first chip includes a first module connection terminal on the first chip along a first side facing the second chip or in an area different from the first chip and facing the second chip. A second side of the second chip includes a second module connection terminal to be connected with the first chip. The first and the second module connection terminals are connected by a bonding wire.Type: GrantFiled: March 30, 2007Date of Patent: February 15, 2011Assignee: Renesas Electronics CorporationInventors: Katsunobu Suzuki, Junichi Iwasaki
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Publication number: 20090140769Abstract: A System-in-Package includes a first chip to be mounted in common for a plurality of product types, a second chip having different specifications for each product type, and a wiring substrate being common to a plurality of product types, on which the first chip and the second chip are to be mounted. A setting signal is supplied from the second chip to the first chip.Type: ApplicationFiled: November 5, 2008Publication date: June 4, 2009Applicant: NEC Electronics CorporationInventors: Katsunobu Suzuki, Takao Ikeuchi, Fumihiko Tajima, Kazuaki Maehara, Hajime Kawamura, Makoto Wakasugi
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Publication number: 20080151484Abstract: A system in package integrating a plurality of semiconductor chips, including a first chip mounted commonly in a plurality of system in packages and at least including a CPU, a second chip having a different specification for each of the plurality of system in packages depending on a connection of internal lines, and a module substrate including the first chip and the second chip adjacent to each other and having a shape common to the plurality of system in packages. The first chip includes a first module connection terminal on the first chip along a first side facing the second chip or in an area different from the first chip and facing the second chip. A second side of the second chip includes a second module connection terminal to be connected with the first chip. The first and the second module connection terminals are connected by a bonding wire.Type: ApplicationFiled: March 30, 2007Publication date: June 26, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Katsunobu Suzuki, Junichi Iwasaki
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Patent number: 7378745Abstract: A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.Type: GrantFiled: August 30, 2005Date of Patent: May 27, 2008Assignees: NEC Electronics Corporation, Denso CorporationInventors: Akimori Hayashi, Katsunobu Suzuki, Ryuichi Oikawa, Makoto Nakagoshi, Naoko Sera, Tadashi Murai, Chiho Ogihara, Ryohei Kataoka, Koji Kondo, Tomohiro Yokochi
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Patent number: 7323238Abstract: In a printed board having a land as an electrode, a colored thermoplastic resin film is arranged on a land forming surface of a thermoplastic resin member so as to set a difference in light reflectivity between the land and the colored thermoplastic resin film, to be greater than that between the land and the thermoplastic resin member. An opening portion is provided in the colored thermoplastic resin film so that at least a part of the land is exposed from the opening portion. Because the colored thermoplastic resin film is positioned on the circumference portion of the opening portion, the difference in light reflectivity of the land with respect to its circumference portion can be effectively increased. As a result, a recognition ratio of the land can be effectively improved.Type: GrantFiled: September 22, 2005Date of Patent: January 29, 2008Assignees: DENSO Corporation, NEC Electronics CorporationInventors: Koji Kondo, Ryohei Kataoka, Tomohiro Yokochi, Makoto Nakagoshi, Tadashi Murai, Akimori Hayashi, Katsunobu Suzuki
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Publication number: 20060068180Abstract: In a printed board having a land as an electrode, a colored thermoplastic resin film is arranged on a land forming surface of a thermoplastic resin member so as to set a difference in light reflectivity between the land and the colored thermoplastic resin film, to be greater than that between the land and the thermoplastic resin member. An opening portion is provided in the colored thermoplastic resin film so that at least a part of the land is exposed from the opening portion. Because the colored thermoplastic resin film is positioned on the circumference portion of the opening portion, the difference in light reflectivity of the land with respect to its circumference portion can be effectively increased. As a result, a recognition ratio of the land can be effectively improved.Type: ApplicationFiled: September 22, 2005Publication date: March 30, 2006Applicants: DENSO CORPORATION, NEC Electronics CorporationInventors: Koji Kondo, Ryohei Kataoka, Tomohiro Yokochi, Makoto Nakagoshi, Tadashi Murai, Akimori Hayashi, Katsunobu Suzuki
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Publication number: 20060044735Abstract: A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.Type: ApplicationFiled: August 30, 2005Publication date: March 2, 2006Applicants: NEC ELECTRONICS CORPORATION, DENSO CORPORATIONInventors: Akimori Hayashi, Katsunobu Suzuki, Ryuichi Oikawa, Makoto Nakagoshi, Naoko Sera, Tadashi Murai, Chiho Ogihara, Ryohei Kataoka, Koji Kondo, Tomohiro Yokochi
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Publication number: 20020096750Abstract: In a package for mounting including a metal plate having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, the recess portion is thinner than the plane portion.Type: ApplicationFiled: March 22, 2002Publication date: July 25, 2002Inventor: Katsunobu Suzuki
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Patent number: 6379996Abstract: In a package for mounting including a metal plate having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, the recess portion is thinner than the plane portion.Type: GrantFiled: April 15, 1999Date of Patent: April 30, 2002Assignee: NEC CorporationInventor: Katsunobu Suzuki
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Patent number: 6150615Abstract: A lead frame used for a semiconductor chip has built-in end resistors accurately patterned through lithographic techniques and an etching from a conductive bonding layer between an insulating film and a conductive metallic foil, the conductive metallic foil is patterned into a conductive island for a semiconductor chip and conductive strips for electric signals, and the built-in end resistors achieve impedance matching for the electric signals.Type: GrantFiled: May 4, 1998Date of Patent: November 21, 2000Assignee: NEC CorporationInventor: Katsunobu Suzuki
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Patent number: 6111311Abstract: The present invention provides a semiconductor package comprising: an electrically conductive base plate having a first surface comprising first, second and third regions; a semiconductor chip provided on the first region of the electrically conductive base plate and the semiconductor chip having at least a first electrode and at least a second electrode; an insulation layer provided on the third region of the electrically conductive base plate; and an electrically conductive thin film pattern laminated on the insulation layer and the electrically conductive thin film pattern being electrically connected to the first electrode of the semiconductor chip, so that the electrically conductive thin film pattern and the first electrode have a first variable potential, wherein the second electrode is connected directly to the second region of the electrically conductive base plate so that the second electrode and the electrically conductive base plate has a second fixed potential which is different from the first vaType: GrantFiled: December 28, 1998Date of Patent: August 29, 2000Assignee: NEC CorporationInventor: Katsunobu Suzuki
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Patent number: 6028358Abstract: A semiconductor package and semiconductor device are provided which enable manufacturing of same with ease of inspection, good reliability, and good thermal characteristics. An insulator made of an organic material and a wiring pattern formed by a metallic foil are formed on top of a metallic base substrate, thereby forming a laminated structure. The metallic base substrate has a plurality of electrically insulated continuity checking terminals. The metallic base substrate, the continuity checking terminals, and the wiring pattern are connected by via holes which pass through the insulator at prescribed locations. The insulator and wiring pattern is removed at a prescribed location at which a semiconductor chip is to be mounted. The exposed metallic base substrate is formed as a cavity of a prescribed depth.Type: GrantFiled: May 30, 1997Date of Patent: February 22, 2000Assignee: NEC CorporationInventor: Katsunobu Suzuki
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Patent number: 5977633Abstract: In the manufacture of a semiconductor device, an insulator film is attached to the back surface of a metal base substrate, and over the insulator film a wiring pattern is formed. A silicon chip is loaded on the metal base substrate via a mount and is connected to the wiring pattern via bonding wires. Solder pads or bump contacts are formed on the wiring pattern; the metal base substrate is locally cut out at areas just above the solder bump contacts to form hollows. Finally the resulting wiring pattern is covered with a cover insulator film and the silicon chip is sealed with seal resin.Type: GrantFiled: May 29, 1998Date of Patent: November 2, 1999Assignee: NEC CorporationInventors: Katsunobu Suzuki, Hiroyuki Uchida
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Patent number: 5889324Abstract: A package for a semiconductor substrate capable of being fabricated with a desirable heat radiation capability. The package includes a laminate metal substrate consisting of a metal plate, an insulator provided on the metal plate, and copper foil provided on the insulator. The metal plate is patterned to form heat spreaders/ground planes and a plurality of solitary land patterns electrically insulated from each other. The copper foil forms wings and an island pattern. The wirings and island pattern are respectively electrically connected to the land patterns and heat spreaders/ground planes by via holes and heat radiation via holes. When the island pattern is provided with ground potential, the heat spreaders/ground planes are also provided with ground potential. At the same time, the heat spreaders/ground planes efficiently release heat output from the rear of an LSI (Large Scaled Integrated Circuit) to the outside of the package.Type: GrantFiled: March 30, 1998Date of Patent: March 30, 1999Assignee: NEC CorporationInventor: Katsunobu Suzuki
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Patent number: 5889325Abstract: A semiconductor device includes an insulation film formed on a metal substrate, wiring patterns formed on the insulation film, and electrodes of a semiconductor chip connected to one ends of the wiring patterns, wherein a plurality of resistors are formed on at least one of surfaces of a front and a back of the insulation film and one ends of the resistors are connected to the electrodes of semiconductor chip through the wiring patterns.Type: GrantFiled: April 24, 1998Date of Patent: March 30, 1999Assignee: NEC CorporationInventors: Hiroyuki Uchida, Katsunobu Suzuki
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Patent number: 5866942Abstract: A laminate package structure for a semiconductor device having a high resistance to humidity, reliability and electrical performance. A polyimide layer and copper foil patterns are formed on a metal base in the form of metal sheet. The metal base comprises a ground pattern maintained at the ground potential, and a plurality of land patterns on which solder balls are formed. The copper foil pattern comprises an island pattern on which an LSI chip is mounted, and an internal wiring patterns connected to electrodes of the LSI chip. The metal base pattern and the internal wiring patterns are electrically interconnected through via-plugs formed in through-holes by an electrolytic plating. A cap is adhesively bonded to the laminated metal base or one of the metal foil patterns.Type: GrantFiled: April 26, 1996Date of Patent: February 2, 1999Assignee: NEC CorporationInventors: Katsunobu Suzuki, Katsuhiko Suzuki, Akira Haga, Isamu Sorimachi, Hiroyuki Uchida
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Patent number: 5844307Abstract: In a plastic molded IC package, a metal pattern and leads are formed on a first surface of an insulating layer, and a conductive pattern connected to a semiconductor chip is formed on a second surface of the insulating layer. The conductive pattern is connected to the leads via through holes in the insulating layer.Type: GrantFiled: July 31, 1996Date of Patent: December 1, 1998Assignee: NEC CorporationInventors: Katsunobu Suzuki, Akira Haga
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Patent number: 5811876Abstract: A lead portion of a film carrier package is sandwiched between a slanted area of a radiation plate and a slanted area of a press frame. The radiation plate has the structures that the front surface thereof has the flat area at the central unit parallel to the back surface, and has at the peripheral portion the slanted area increasing or decreasing the thickness toward the outer periphery of the radiation plate. The film carrier package has the structures that a window is formed at the central area thereof, having a size smaller than the flat area, a slit is formed in an insulating film inside of the interconnection pattern by 1 to 5 mm, and the area surrounded by slits at the four sides is larger than the outer dimension of the radiation plate. The slanted area of the radiation plate engages with the slanted area of the press frame. The film carrier package with the radiation plate can be assembled in a short period while ensuring a low heat resistance.Type: GrantFiled: April 23, 1996Date of Patent: September 22, 1998Assignee: NEC CorporationInventors: Akira Haga, Katsunobu Suzuki
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Patent number: 5783426Abstract: The semiconductor device disclosed has a cap in which, at an undersurface periphery portion, a plurality of looped projections are formed for intercepting a continuous bubble path that may be formed for a gas to escape. The preparatory stage steps of assembling the device includes forming a plated layer on a lead frame, adhesively fixing the lead frame on a base plate, cutting and separating leads from the lead frame, and shaping the leads into a predetermined form. The assembling stage steps of the device includes mounting a semiconductor chip on the base plate and bonding electrodes on the semiconductor chip and the leads, and mounting the cap which has the looped projections for intercepting a continuous bubble path that may be formed for a gas to escape. Since the steps such as forming a plated layer and shaping the leads have been completed in the preparatory stage, the assembling steps which include the mounting of the cap having the looped projections can be efficiently carried out.Type: GrantFiled: August 7, 1995Date of Patent: July 21, 1998Assignee: NEC CorporationInventors: Katsuhiko Suzuki, Isamu Sorimachi, Akira Haga, Hiroyuki Uchida, Katsunobu Suzuki