Patents by Inventor Katsunori Hirota

Katsunori Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11605665
    Abstract: A semiconductor apparatus includes a semiconductor layer that includes a photoelectric conversion unit disposed between a front surface and a back surface and a transistor disposed at the front surface, and a dielectric film in contact with the back surface, wherein the semiconductor layer includes a region extending 100 nm from the back surface, the region having boron concentrations whose maximum value is more than 1×1020 [atoms/cm3].
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: March 14, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsunori Hirota, Tsutomu Tange, Takuya Hara
  • Patent number: 11502162
    Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer overlapping the first semiconductor layer, and a wiring structure arranged between them. The second semiconductor layer is provided with p-type MIS transistor. A crystal structure of the first semiconductor layer has a first crystal orientation and a second crystal orientation in direction along a principal surface of the first semiconductor layer. A Young's modulus of the first semiconductor layer in a direction along the first crystal orientation is higher than that in a direction along the second crystal orientation. An angle formed by the first crystal orientation and a direction in which a source and a drain of the p-type MIS transistor are arranged is more than 30 degrees and less than 60 degrees, and an angle formed by the second crystal orientation and that direction is 0 degrees or more and 30 degrees or less.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 15, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takumi Ogino, Katsunori Hirota, Hiroaki Kobayashi
  • Patent number: 11276723
    Abstract: A semiconductor device comprising: a substrate; a semiconductor layer; and a wiring structure section between the substrate and the semiconductor layer, the wiring structure section including a plurality of stacked wiring layers and a plurality of stacked insulating films, the wiring structure section including an electrode, wherein an opening for connecting a member to the electrode is formed in the semiconductor layer and the wiring structure section; the semiconductor layer has an isolation region in which an insulating film is embedded and which surrounds the opening; the wiring structure section has a ring which is formed of the plurality of wiring layers and surround the opening; and a distance between the opening and the ring closest to the opening is larger than a distance between the opening and the isolation region closest to the opening.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: March 15, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takumi Ogino, Hideaki Ishino, Akihiro Shimizu, Katsunori Hirota, Tsutomu Tange
  • Publication number: 20210175324
    Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer overlapping the first semiconductor layer, and a wiring structure arranged between them. The second semiconductor layer is provided with p-type MIS transistor. A crystal structure of the first semiconductor layer has a first crystal orientation and a second crystal orientation in direction along a principal surface of the first semiconductor layer. A Young's modulus of the first semiconductor layer in a direction along the first crystal orientation is higher than that in a direction along the second crystal orientation. An angle formed by the first crystal orientation and a direction in which a source and a drain of the p-type MIS transistor are arranged is more than 30 degrees and less than 60 degrees, and an angle formed by the second crystal orientation and that direction is 0 degrees or more and 30 degrees or less.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 10, 2021
    Inventors: Takumi Ogino, Katsunori Hirota, Hiroaki Kobayashi
  • Publication number: 20210126026
    Abstract: A semiconductor apparatus includes a semiconductor layer that includes a photoelectric conversion unit disposed between a front surface and a back surface and a transistor disposed at the front surface, and a dielectric film in contact with the back surface, wherein the semiconductor layer includes a region extending 100 nm from the back surface, the region having boron concentrations whose maximum value is more than 1×1020 [atoms/cm3].
    Type: Application
    Filed: October 21, 2020
    Publication date: April 29, 2021
    Inventors: Katsunori Hirota, Tsutomu Tange, Takuya Hara
  • Patent number: 10991741
    Abstract: A silicon compound film that is any one of a silicon oxide film, a silicon nitride film, and a silicon carbide film, and a metal compound film lying between the silicon compound film and a semiconductor layer are arranged above a main face. The silicon compound film and the metal compound film extend into a first trench, and the metal compound film extends into a second trench. When a distance from the bottom of the second trench to the silicon compound film is expressed as “Hb”, and a distance from the main face to the silicon compound film is expressed as “Hd”, the respective distances satisfy the condition “Hd<Hb”.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 27, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshiei Tanaka, Katsunori Hirota, Yusuke Onuki, Tsutomu Tange, Takumi Ogino
  • Patent number: 10916574
    Abstract: An imaging device includes a substrate including a photoelectric conversion portion and an insulating layer formed to cover at least a part of the photoelectric conversion portion. The insulating layer contains silicon, nitrogen, and chlorine. In an embodiment, in at least a part of the insulating layer, a ratio of silicon atoms bonded to one, two, or three nitrogen atoms and not bonded to an oxygen atom is not more than 20% in silicon atoms contained in at least the part.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: February 9, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takahiro Suzuki, Yoshiei Tanaka, Tsutomu Tange, Katsunori Hirota
  • Patent number: 10777596
    Abstract: An imaging apparatus includes a substrate including a photoelectric conversion portion; and a silicon nitride layer arranged to cover at least a portion of the photoelectric conversion portion. The silicon nitride layer contains chlorine. An N/Si composition ratio in the silicon nitride layer is not less than 1.00 and is less than 1.33.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 15, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Katsunori Hirota, Keiichi Sasaki, Tsutomu Tange, Yoshiei Tanaka, Akira Ohtani
  • Publication number: 20200127032
    Abstract: A semiconductor device comprising: a substrate; a semiconductor layer; and a wiring structure section between the substrate and the semiconductor layer, the wiring structure section including a plurality of stacked wiring layers and a plurality of stacked insulating films, the wiring structure section including an electrode, wherein an opening for connecting a member to the electrode is formed in the semiconductor layer and the wiring structure section; the semiconductor layer has an isolation region in which an insulating film is embedded and which surrounds the opening; the wiring structure section has a ring which is formed of the plurality of wiring layers and surround the opening; and a distance between the opening and the ring closest to the opening is larger than a distance between the opening and the isolation region closest to the opening.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 23, 2020
    Inventors: Takumi Ogino, Hideaki Ishino, Akihiro Shimizu, Katsunori Hirota, Tsutomu Tange
  • Publication number: 20200083263
    Abstract: A silicon compound film that is any one of a silicon oxide film, a silicon nitride film, and a silicon carbide film, and a metal compound film lying between the silicon compound film and a semiconductor layer are arranged above a main face. The silicon compound film and the metal compound film extend into a first trench, and the metal compound film extends into a second trench. When a distance from the bottom of the second trench to the silicon compound film is expressed as “Hb”, and a distance from the main face to the silicon compound film is expressed as “Hd”, the respective distances satisfy the condition “Hd<Hb”.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 12, 2020
    Inventors: Yoshiei Tanaka, Katsunori Hirota, Yusuke Onuki, Tsutomu Tange, Takumi Ogino
  • Publication number: 20190280023
    Abstract: An imaging device includes a substrate including a photoelectric conversion portion and an insulating layer formed to cover at least a part of the photoelectric conversion portion. The insulating layer contains silicon, nitrogen, and chlorine. In an embodiment, in at least a part of the insulating layer, a ratio of silicon atoms bonded to one, two, or three nitrogen atoms and not bonded to an oxygen atom is not more than 20% in silicon atoms contained in at least the part.
    Type: Application
    Filed: February 14, 2019
    Publication date: September 12, 2019
    Inventors: Takahiro Suzuki, Yoshiei Tanaka, Tsutomu Tange, Katsunori Hirota
  • Publication number: 20190096946
    Abstract: An imaging apparatus includes a substrate including a photoelectric conversion portion; and a silicon nitride layer arranged to cover at least a portion of the photoelectric conversion portion. The silicon nitride layer contains chlorine. An N/Si composition ratio in the silicon nitride layer is not less than 1.00 and is less than 1.33.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 28, 2019
    Inventors: Katsunori Hirota, Keiichi Sasaki, Tsutomu Tange, Yoshiei Tanaka, Akira Ohtani
  • Patent number: 10103186
    Abstract: A photoelectric conversion section contains a semiconductor element having a laminated structure which contains an electroconductor, a semiconductor, and an insulator provided between the electroconductor and the semiconductor, in which the insulator is a silicon oxide film containing nitrogen in a main portion located between the electroconductor and the semiconductor.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 16, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Katsunori Hirota
  • Publication number: 20180070041
    Abstract: A solid-state image sensor is provided. The solid-state image sensor comprises a pixel region including a photoelectric conversion unit formed in a substrate. A first silicon nitride layer is arranged to cover at least part of the photoelectric conversion unit, and a concentration of chlorine contained in the first silicon nitride layer falls within a range of 1 atomic % to 3 atomic %.
    Type: Application
    Filed: August 9, 2017
    Publication date: March 8, 2018
    Inventors: Katsunori Hirota, Toshihide Kimura, Hideaki Ishino
  • Patent number: 9859329
    Abstract: There is provided an imaging device manufacturing method contributing to improved reliability and yield. The method includes forming a first insulating film on a polysilicon film and then removing a portion of the first insulating film formed on a second main surface and a portion of the first insulating film formed on a side surface of the substrate to expose a polysilicon film. After the polysilicon film is exposed, a second insulating film is formed on the first main surface by a plasma chemical vapor deposition (CVD) method.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 2, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsunori Hirota, Satoshi Ogawa, Nobutaka Ukigaya
  • Patent number: 9812484
    Abstract: An image pickup apparatus includes a semiconductor layer that constitutes a pixel circuit region and a peripheral circuit region. An element isolation portion is disposed in the pixel circuit region and the peripheral circuit region, defines an element portion of the semiconductor layer, and contains an insulator. The element isolation portion in the pixel circuit region has a hydrogen concentration 10 times or more higher than the hydrogen concentration of the element isolation portion in the peripheral circuit region.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 7, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideaki Ishino, Katsunori Hirota
  • Patent number: 9773833
    Abstract: A photoelectric conversion apparatus includes a charge accumulation region of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the second conductivity type, and an element isolation. The first semiconductor region is arranged so as to extend downward from a portion between the charge accumulation region and the element isolation, and the second semiconductor region includes a portion arranged below the charge accumulation region, and impurity concentration distributions of the charge accumulation region, the first semiconductor region and the second semiconductor region in a depth direction respectively have peaks at depth Rp1, Rp2, and Rp3, and Rp1<Rp2<Rp3 is satisfied. Impurity concentration C1 of the first semiconductor region at Rp2 is higher than impurity concentration C2 of the second semiconductor region at Rp3.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 26, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Katsunori Hirota
  • Publication number: 20170179191
    Abstract: There is provided an imaging device manufacturing method contributing to improved reliability and yield. The method includes forming a first insulating film on a polysilicon film and then removing a portion of the first insulating film formed on a second main surface and a portion of the first insulating film formed on a side surface of the substrate to expose a polysilicon film. After the polysilicon film is exposed, a second insulating film is formed on the first main surface by a plasma chemical vapor deposition (CVD) method.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 22, 2017
    Inventors: Katsunori Hirota, Satoshi Ogawa, Nobutaka Ukigaya
  • Patent number: 9570506
    Abstract: A photoelectric conversion device includes a pixel circuit section including: a first semiconductor region containing a first conductivity type impurity; a second semiconductor region formed in the first semiconductor region by using the first conductivity type impurity; a third semiconductor region formed in the second semiconductor region by using a second conductivity type impurity; and a contact plug formed on the third semiconductor region. A net concentration of the first conductivity type impurity is higher in the second semiconductor region than in the first and third semiconductor regions. In the second and third semiconductor regions, a distance between the contact plug and a position where the concentration of the second conductivity type impurity is maximum is equal to or less than a distance between the contact plug and a position where the concentration of the first conductivity type impurity is maximum.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: February 14, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Endo, Katsunori Hirota, Takumi Ogino, Masashi Kusukawa, Seiichi Tamura
  • Publication number: 20160343750
    Abstract: An image pickup apparatus includes a semiconductor layer that constitutes a pixel circuit region and a peripheral circuit region. An element isolation portion is disposed in the pixel circuit region and the peripheral circuit region, defines an element portion of the semiconductor layer, and contains an insulator. The element isolation portion in the pixel circuit region has a hydrogen concentration 10 times or more higher than the hydrogen concentration of the element isolation portion in the peripheral circuit region.
    Type: Application
    Filed: May 17, 2016
    Publication date: November 24, 2016
    Inventors: Hideaki Ishino, Katsunori Hirota