Patents by Inventor Katsunori Onishi

Katsunori Onishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200318342
    Abstract: An H-beam joint structure for joining ends of H-beam steel materials adjacent to each other. The steel materials have a flange and a web. The joint structure includes: a transmission plate arranged parallel to a front surface of the web on at least one side of the web of the H-beam and the steel material, and welded to a back surface of the flange; and a coupling plate provided in close contact with the transmission plate to connect the H-beam and the steel material. A web of the H-beam, the web of the steel material and the transmission plate are bolted via the coupling plate. As a result, there is provided an H-beam joint structure which has a joining strength equivalent to a conventional joint structure for an H-beam, and also which can easily be constructed to have less parts and make front surfaces of the flanges flat.
    Type: Application
    Filed: October 11, 2018
    Publication date: October 8, 2020
    Inventor: Katsunori ONISHI
  • Patent number: 10741668
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bala Haran, Ruilong Xie, Balaji Kannan, Katsunori Onishi, Vimal K. Kamineni
  • Patent number: 10658363
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Kannan, Ayse M. Ozbek, Tao Chu, Bala Haran, Vishal Chhabra, Katsunori Onishi, Guowei Xu
  • Publication number: 20200056370
    Abstract: A coupling structure in which two structure members (1, 2) are connected to each other. The structure members integrally have projecting parts (32, 42) projecting from one side part (A side or B side) thereof, respectively. The two structure members are close to each other, and the projecting parts overlap the side parts of the counterpart structure members (2, 1) so as to be positioned on sides opposite to each other, respectively. The projecting parts and the side parts of the counterpart structure members are each fixed by bolt joint. Thus, mainly, it is possible to provide a coupling in which the number of components used for connecting the structure members to each other is reduced, projection from (flange parts of) the structure members is eliminated, and construction is easily performed.
    Type: Application
    Filed: March 6, 2018
    Publication date: February 20, 2020
    Inventors: Miki HEBIISHI, Katsunori ONISHI
  • Publication number: 20190393221
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Inventors: Balaji KANNAN, Ayse M. OZBEK, Tao CHU, Bala HARAN, Vishal CHHABRA, Katsunori ONISHI, Guowei XU
  • Patent number: 10446550
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Kannan, Ayse M. Ozbek, Tao Chu, Bala Haran, Vishal Chhabra, Katsunori Onishi, Guowei Xu
  • Patent number: 10354928
    Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj Kumar Patil, Katsunori Onishi, Pei Liu, Chih-Chiang Chang
  • Publication number: 20190131424
    Abstract: The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a first and second dummy gate over a fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer and a second gate spacer, the opening exposing a source/drain region; recessing the first and second gate spacers; forming an etch stop layer within the opening such that the etch stop layer extends vertically along the recessed first and second gate spacers; forming a dielectric fill over the etch stop layer to substantially fill the opening; replacing the first and second dummy gates with first and second RMG structures; recessing the first and second RMG structures; and forming a gate cap layer over the first and second RMG structures.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 2, 2019
    Inventors: Guowei Xu, Suraj K. Patil, Hui Zang, Katsunori Onishi, Keith H. Tabakman
  • Publication number: 20190115346
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Inventors: Balaji KANNAN, Ayse M. OZBEK, Tao CHU, Bala HARAN, Vishal CHHABRA, Katsunori ONISHI, Guowei XU
  • Publication number: 20190096679
    Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Balaji Kannan, Bala Haran, Vimal K. Kamineni, Sungkee Han, Neal Makela, Suraj K. Patil, Pei Liu, Chih-Chiang Chang, Katsunori Onishi, Keith Kwong Hon Wong, Ruilong Xie, Chanro Park, Min Gyu Sung
  • Patent number: 10242982
    Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Katsunori Onishi, Tek Po Rinus Lee
  • Publication number: 20190027578
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.
    Type: Application
    Filed: July 19, 2017
    Publication date: January 24, 2019
    Inventors: Bala HARAN, Ruilong XIE, Balaji KANNAN, Katsunori ONISHI, Vimal K. KAMINENI
  • Publication number: 20180323113
    Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.
    Type: Application
    Filed: July 18, 2018
    Publication date: November 8, 2018
    Inventors: Suraj Kumar PATIL, Katsunori ONISHI, Pei LIU, Chih-Chiang CHANG
  • Publication number: 20180261595
    Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 13, 2018
    Inventors: Ruilong Xie, Katsunori Onishi, Tek Po Rinus Lee
  • Patent number: 10056303
    Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj Kumar Patil, Katsunori Onishi, Pei Liu, Chih-Chiang Chang
  • Publication number: 20170338325
    Abstract: We disclose a semiconductor device, comprising a semiconductor substrate; at least one gate structure disposed above the semiconductor substrate, wherein the gate structure comprises a gate structure cavity partially filled with at least one metal layer; and an ultraviolet (UV) cured high density plasma (HDP) nitride cap layer in the gate structure cavity above the at least one metal layer. We also disclose at least one method and at least one system by which the semiconductor device may be formed. The UV cured HDP nitride cap layer may be substantially free of voids or seams, and as a result, the semiconductor device may have a reduced Vt shift relative to comparable semiconductor devices known in the art.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Huy Cao, Chih-Chiang Chang, Katsunori Onishi, Songkram Srivathanakul
  • Patent number: 9761679
    Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Chang, Katsunori Onishi, Jian Yu
  • Patent number: 9735058
    Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Chang, Katsunori Onishi, Jian Yu
  • Publication number: 20160322258
    Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 3, 2016
    Inventors: Paul CHANG, Katsunori ONISHI, Jian YU
  • Patent number: 9455195
    Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Chang, Katsunori Onishi, Jian Yu