Abstract: A 4-2 compressor circuit calculates the sum of first through fourth inputs and a carry input applied thereto and for furnishing the summation result and first and second carries generated during the calculation of the summation. An input value converting unit inverts the third and fourth inputs only if the third input is logic 0 and the fourth input is logic 1. A summation unit calculates the logical exclusive OR of any two of the first through fourth inputs and the carry input applied to the 4-2 compressor circuit, the logical exclusive OR of any two of the first logical exclusive OR and the remaining three inputs, the logical exclusive OR of any two of the second logical exclusive OR and the remainder, and the logical exclusive OR of the third logical exclusive OR and the remainder. The summation unit then furnishes the fourth logical exclusive OR as the summation result. A carry calculating unit calculates the first carry from the first, third, and fourth inputs.

Abstract: A co-ordinates input device having a transparent substrate member is composed of: a transparent substrate; an ITO film formed on a surface of the transparent substrate; a pair of electrodes formed at a given distance from each other on the ITO film; an operation region formed between the pair of electrodes; and lead electrodes, extending from the pair of electrodes, formed on the ITO film; in which at least one of the lead electrodes extending from the pair of electrodes is formed on the ITO film on a side of the operation region, and between the lead electrode and the operation region, a groove is formed in the ITO film alone or in the ITO film and continuously extending into the transparent substrate.

Abstract: A clock generator including a frequency multiplier, a phase lock circuit and a frequency divider. The frequency multiplier generates a frequency multiplied clock by multiplying the frequency of an input clock. The phase lock circuit detects a phase difference between the input clock and a frequency divided clock, and generates, by delaying the frequency multiplied clock by an amount corresponding to the phase difference, a phase-locked clock with its phase locked with the input clock. The frequency divider detects in every fixed cycle a particular pulse of the phase-locked clock, and generates the frequency divided clock by dividing the phase-locked clock with reference to the particular pulse of the phase-locked clock. In particular, the frequency divider detects the particular pulse immediately previous to a falling edge of the input clock.

Abstract: In a microprocesssor (101), a selector (7) is connected to a bus ID <0:127> through a write buffer (5) and a DRAM (27), a cache (28) and an IQ (8) are also connected to the bus ID <0:127>. The bus ID <0:127> and the microprocessor (101) are connected to the external memory (4) and the external bus master (41) with a data bus D <0:15> through a BIU (3). The microprocessor (101) is also connected to the external memory (4) and the external bus master (41) with an address bus (58) and control bus (57). The BIU (3) controls an access to a memory integrated in the microprocessor (101) and a memory externally connected thereto. With this configuration, the DRAM and the cache can be integrated together in the microprocessor which is externally connected to the bus master.

Abstract: A clock generating circuit includes a plurality of delay lines connected in cascade, each delay line including two switching elements for letting in or shutting out a clock, and a delay element connected to each of the switching elements. A PLL circuit and a semiconductor device both include the clock generating circuit. The number K of the delay units in each of the delay lines of the clock generating circuit is calculated from:K>?{1/(2.multidot.N.multidot.F.sub.ref)}-(T.sub.mul)!/(T.sub.

Abstract: A microcomputer which comprises a processor and a memory integrated on one chip wherein the memory is arranged in a plurality of memory cell region rows, and a processor is arranged between the memory cell region rows. A microcomputer wherein the memory cell regions are connected to each other row by row through a bus each of which is connected to the processor.

Abstract: A cache memory, which is provided with means for prohibiting generation of an external bus cycle to read the data to be accessed from a main storage and means for prohibiting update of the content of a tag memory when a cache miss is generated under a test mode of its test function in order to shorten the test time by omitting the process of resetting test patterns in both the tag memory and a data memory.