Patents by Inventor Katsunori Shibuya
Katsunori Shibuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240003762Abstract: A functional film includes a strain resistance film provided on one principal surface of a flexible insulating base. The strain resistance film is a chromium nitride thin-film having a thickness of 150 nm or less. In an X-ray diffraction chart with a CuK? ray as an X-ray source, the strain resistance film has an intensity ratio I2/I1 of 0.001 or more, where the intensity ratio I2/I1 is a ratio of the intensity I2 of the second peak in a range in which 2? is 60° to 65° to the intensity I1 of the first peak in a range in which 2? is 43° to 45°. The strain resistance film is less liable to crack due to bending, and has a high gauge factor. The functional film is suitably used for a strain sensor.Type: ApplicationFiled: October 25, 2021Publication date: January 4, 2024Inventors: Satoshi YASUI, Katsunori SHIBUYA, Kazuhiro NAKAJIMA
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Publication number: 20220364937Abstract: Provided is an electroconductive film having a metal thin-film on a resin film base; and a temperature sensor film which is obtained by patterning the metal thin-film on the resin film base. An electroconductive film (101) which is used for the production of a temperature sensor film comprises a metal thin-film (10) on one principal surface of a resin film base (50), with a chromium oxide thin-film (21) serving as an underlying layer interposed therebetween. A temperature sensor film is obtained by patterning the metal thin-film so as to form a thermometric resistor part and a lead part that is connected to the thermometric resistor part.Type: ApplicationFiled: September 16, 2020Publication date: November 17, 2022Applicant: NITTO DENKO CORPORATIONInventors: Katsunori Shibuya, Kazuhiro Nakajima, Kodai Miyamoto
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Publication number: 20220349760Abstract: Provided is a temperature sensor film comprising a metal-thin film patterned on a resin film substrate, and having high temperature measurement accuracy. A conductive film (102) that is used for producing a temperature sensor film has a nickel thin film (10) on one principal surface of a resin film substrate (50). It is preferable that the interplanar spacing of nickel (111) plane in the nickel thin-film is less than 0.2040 nm. The temperature sensor film is obtained by patterning the nickel thin film to form a temperature-measuring resistance part and a lead part connected to the temperature-measuring resistance part.Type: ApplicationFiled: September 16, 2020Publication date: November 3, 2022Applicant: NITTO DENKO CORPORATIONInventors: Satoshi Yasui, Kodai Miyamoto, Katsunori Shibuya
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Patent number: 10312197Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer.Type: GrantFiled: September 2, 2014Date of Patent: June 4, 2019Assignee: Toshiba Memory CorporationInventors: Yuusuke Takano, Takashi Imoto, Takeshi Watanabe, Soichi Homma, Katsunori Shibuya
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Patent number: 9824905Abstract: A semiconductor manufacturing device has an upper cover configured to be arranged above top surface of unshielded semiconductor device which are mounted on a tray placed on a carrier to go through electromagnetic shielding, and a displacement detector configured to detect an abnormality when the upper cover is raised by at least one of the semiconductor device which is brought into contact with a bottom surface of the upper cover.Type: GrantFiled: September 10, 2014Date of Patent: November 21, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
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Patent number: 9646908Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.Type: GrantFiled: July 22, 2016Date of Patent: May 9, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Soichi Homma, Masaya Shima, Yuusuke Takano, Takeshi Watanabe, Katsunori Shibuya
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Publication number: 20170025321Abstract: In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching.Type: ApplicationFiled: July 22, 2016Publication date: January 26, 2017Inventors: Soichi HOMMA, Masaya SHIMA, Yuusuke TAKANO, Takeshi WATANABE, Katsunori SHIBUYA
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Patent number: 9458535Abstract: A semiconductor manufacturing device has a conveyor configured to convey a tray having an unshielded semiconductor device mounted thereon to go through electromagnetic shielding, and a controller configured to control the conveyor. The controller performs control to take out the tray from a tray supply storage storing trays each having an unshielded semiconductor device mounted thereon to go through the electromagnetic shielding, place the tray on a carrier, and convey this carrier to a sputtering device which coats the unshielded semiconductor device with a sputtering material for the electromagnetic shielding, and the controller performs control to take out, from the sputtering device, the carrier having the tray placed thereon with an electromagnetically shielded semiconductor device being mounted on the tray, convey the tray, pick up the tray having the electromagnetically shielded semiconductor device mounted thereon from the carrier, and store the tray in the tray supply storage.Type: GrantFiled: September 10, 2014Date of Patent: October 4, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
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Patent number: 9385090Abstract: A semiconductor device includes a conductive shield layer that has a first portion covering a surface of a sealing resin layer and a second portion covering side surfaces of the sealing resin layer and side surfaces of the substrate. Portions of wiring layers, including a grounding wire, on or in the substrate have cut planes which are exposed to the side surfaces of the substrate and spread out in a thickness direction of the substrate. A cut plane of the grounding wire is electrically connected to the shield layer. An area of the cut plane of the grounding wire is larger than an area of a cross section of the grounding wire parallel to, and inward of the substrate from, the cut plane of the grounding wire.Type: GrantFiled: September 2, 2014Date of Patent: July 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
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Patent number: 9349694Abstract: According to one embodiment, a semiconductor device includes a substrate. A semiconductor chip is disposed on a first surface of the substrate. The semiconductor chip is covered with a sealing material. A front surface and a side surface of the sealing material are covered with a conductive film. On an outer edge of a substrate-side of the semiconductor device, a step or a trench is formed.Type: GrantFiled: August 29, 2014Date of Patent: May 24, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Katsunori Shibuya, Soichi Homma, Yuusuke Takano, Shinpei Ishida
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Publication number: 20150170988Abstract: According to one embodiment, a plurality of semiconductor devices is mounted on a wiring substrate. A surface, on which a semiconductor devices of the wiring substrate are mounted, and the plurality of semiconductor devices are sealed by using a sealing resin. The wiring substrate which is sealed is cut and thus separated into semiconductor apparatuses. The semiconductor apparatuses after the separation are heated. A shield layer is formed by metal sputtering over wiring exposed at the edge of the cut wiring substrate and the sealing resin of the semiconductor apparatus, after the heating.Type: ApplicationFiled: September 2, 2014Publication date: June 18, 2015Inventors: Takeshi WATANABE, Takashi IMOTO, Yuusuke TAKANO, Soichi HOMMA, Katsunori SHIBUYA
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Publication number: 20150167156Abstract: A semiconductor manufacturing device has a conveyor configured to convey a tray having an unshielded semiconductor device mounted thereon to go through electromagnetic shielding, and a controller configured to control the conveyor. The controller performs control to take out the tray from a tray supply storage storing trays each having an unshielded semiconductor device mounted thereon to go through the electromagnetic shielding, place the tray on a carrier, and convey this carrier to a sputtering device which coats the unshielded semiconductor device with a sputtering material for the electromagnetic shielding, and the controller performs control to take out, from the sputtering device, the carrier having the tray placed thereon with an electromagnetically shielded semiconductor device being mounted on the tray, convey the tray, pick up the tray having the electromagnetically shielded semiconductor device mounted thereon from the carrier, and store the tray in the tray supply storage.Type: ApplicationFiled: September 10, 2014Publication date: June 18, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Katsunori SHIBUYA, Takashi IMOTO, Soichi HOMMA, Takeshi WATANABE, Yuusuke TAKANO
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Publication number: 20150167157Abstract: A semiconductor manufacturing device has an upper cover configured to be arranged above top surface of unshielded semiconductor device which are mounted on a tray placed on a carrier to go through electromagnetic shielding, and a displacement detector configured to detect an abnormality when the upper cover is raised by at least one of the semiconductor device which is brought into contact with a bottom surface of the upper cover.Type: ApplicationFiled: September 10, 2014Publication date: June 18, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsunori Shibuya, Takashi Imoto, Soichi Homma, Takeshi Watanabe, Yuusuke Takano
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Publication number: 20150171020Abstract: A semiconductor device includes a conductive shield layer that has a first portion covering a surface of a sealing resin layer and a second portion covering side surfaces of the sealing resin layer and side surfaces of the substrate. Portions of wiring layers, including a grounding wire, on or in the substrate have cut planes which are exposed to the side surfaces of the substrate and spread out in a thickness direction of the substrate. A cut plane of the grounding wire is electrically connected to the shield layer. An area of the cut plane of the grounding wire is larger than an area of a cross section of the grounding wire parallel to, and inward of the substrate from, the cut plane of the grounding wire.Type: ApplicationFiled: September 2, 2014Publication date: June 18, 2015Inventors: Katsunori SHIBUYA, Takashi IMOTO, Soichi HOMMA, Takeshi WATANABE, Yuusuke TAKANO
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Publication number: 20150171019Abstract: According to one embodiment, a semiconductor device includes a substrate. A semiconductor chip is disposed on a first surface of the substrate. The semiconductor chip is covered with a sealing material. A front surface and a side surface of the sealing material are covered with a conductive film. On an outer edge of a substrate-side of the semiconductor device, a step or a trench is formed.Type: ApplicationFiled: August 29, 2014Publication date: June 18, 2015Inventors: Katsunori SHIBUYA, Soichi HOMMA, Yuusuke TAKANO, Shinpei ISHIDA
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Publication number: 20150171021Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer.Type: ApplicationFiled: September 2, 2014Publication date: June 18, 2015Inventors: Yuusuke TAKANO, Takashi IMOTO, Takeshi WATANABE, Soichi HOMMA, Katsunori SHIBUYA
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Publication number: 20120286411Abstract: According to one embodiment, there is provided a semiconductor device including a wiring board, a semiconductor chip mounted on a first surface of the wiring board, first external electrodes provided on the first surface of the wiring board, second external electrodes provided on a second surface of the wiring board, and a sealing resin layer sealing the semiconductor chip together with the first external electrodes. The sealing resin layer has a recessed portion exposing a part of each of the first external electrodes. The plural semiconductor devices are stacked to form a semiconductor module with a POP structure. In this case, the first external electrodes of the lower-side semiconductor device and the second external electrodes of the upper-side semiconductor device are electrically connected.Type: ApplicationFiled: March 16, 2012Publication date: November 15, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi Watanabe, Takashi Imoto, Naoto Takebe, Yuuki Kuro, Yusuke Doumae, Katsunori Shibuya, Yoshimune Kodama, Yuji Karakane, Masatoshi Kawato