Patents by Inventor Katsuo Arai
Katsuo Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140264383Abstract: A semiconductor device includes a die pad, an SiC chip mounted on the die pad, a porous first sintered Ag layer bonding the die pad and the SiC chip, and a reinforcing resin portion covering a surface of the first sintered Ag layer and formed in a fillet shape. The semiconductor device further includes a source lead electrically connected to a source electrode of the SiC chip, a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body which covers the SiC chip, the first sintered Ag layer, and a part of the die pad, and the reinforcing resin portion covers a part of a side surface of the SiC chip.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryoichi KAJIWARA, Takuya NAKAJO, Katsuo ARAI, Yuichi YATO, Hiroi OKA, Hiroshi HOZOJI
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Patent number: 8492202Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.Type: GrantFiled: November 15, 2012Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
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Patent number: 8314484Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.Type: GrantFiled: January 21, 2010Date of Patent: November 20, 2012Assignee: Renesas Electronics CorporationInventors: Ryoichi Kajiwara, Shigehisa Motowaki, Kazutoshi Ito, Toshiaki Ishii, Katsuo Arai, Takuya Nakajo, Hidemasa Kagii
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Patent number: 8114710Abstract: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip.Type: GrantFiled: January 23, 2009Date of Patent: February 14, 2012Assignee: Renesas Electronics CorporationInventors: Akira Muto, Nobuya Koike, Katsuo Arai, Atsushi Fujiki
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Publication number: 20100187678Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.Type: ApplicationFiled: January 21, 2010Publication date: July 29, 2010Applicant: Renesas Technology Corp.Inventors: Ryoichi KAJIWARA, Shigehisa MOTOWAKI, Kazutoshi ITO, Toshiaki ISHII, Katsuo ARAI, Takuya NAKAJO, Hidemasa KAGII
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Publication number: 20090215230Abstract: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip.Type: ApplicationFiled: January 23, 2009Publication date: August 27, 2009Inventors: Akira MUTO, Nobuya Koike, Katsuo Arai, Atsushi Fujiki
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Publication number: 20080268577Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.Type: ApplicationFiled: June 30, 2008Publication date: October 30, 2008Inventors: Hidemasa KAGII, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Publication number: 20080220568Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.Type: ApplicationFiled: May 8, 2008Publication date: September 11, 2008Inventors: Akira MUTO, Ichio Shimizu, Katsuo Arai, Hidemasa Kagii, Hiroshi Sato, Hiroyuki Nakamura, Takuya Nakajo, Keiichi Okawa, Masahiko Osaka
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Patent number: 7405469Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.Type: GrantFiled: April 13, 2007Date of Patent: July 29, 2008Assignee: Renesas Technology Corp.Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Patent number: 7374965Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.Type: GrantFiled: February 7, 2006Date of Patent: May 20, 2008Assignee: Renesas Technology Corp.Inventors: Akira Muto, Ichio Shimizu, Katsuo Arai, Hidemasa Kagii, Hiroshi Sato, Hiroyuki Nakamura, Takuya Nakajo, Keiichi Okawa, Masahiko Osaka
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Publication number: 20070210430Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals 6G, 6S via connection materials 5b, 5c. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals 6G, 6S being exposed. Mounting surfaces of the metal plate terminals 6G, 6S and a third part of the metal cap are bonded to electrodes on a mounting board 10 via connection materials 5e, 5f and 5g.Type: ApplicationFiled: April 13, 2007Publication date: September 13, 2007Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Patent number: 7220617Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals. In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.Type: GrantFiled: February 8, 2006Date of Patent: May 22, 2007Assignee: Renesas Technology, Corp.Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Publication number: 20060175700Abstract: A semiconductor chip is sealed by resin without covering an outer terminal of a semiconductor device having a power transistor. A semiconductor chip having a power transistor is housed within a recess of a metal cap while a drain electrode on a first surface of the semiconductor chip is bonded to a bottom of the recess via a connection material. A gate electrode and a source electrode are formed on a second surface opposite to the first surface of the semiconductor chip, and the gate electrode and the source electrode are bonded with metal plate terminals In addition, the semiconductor chip is sealed by a resin sealing body with mounting-surfaces of the metal plate terminals being exposed. Mounting surfaces of the metal plate terminals and a third part of the metal cap are bonded to electrodes on a mounting board.Type: ApplicationFiled: February 8, 2006Publication date: August 10, 2006Inventors: Hidemasa Kagii, Akira Muto, Ichio Shimizu, Katsuo Arai, Hiroshi Sato, Hiroyuki Nakamura, Masahiko Osaka, Takuya Nakajo, Keiichi Okawa, Hiroi Oka
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Publication number: 20060177967Abstract: A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion.Type: ApplicationFiled: February 7, 2006Publication date: August 10, 2006Inventors: Akira Muto, Ichio Shimizu, Katsuo Arai, Hidemasa Kagii, Hiroshi Sato, Hiroyuki Nakamura, Takuya Nakajo, Keiichi Okawa, Masahiko Osaka
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Patent number: 6838315Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a substrate in which a plurality of electrode members are individually placed on one main surface thereof in separated form, a step of placing a semiconductor chip on the one main surface of the substrate and electrically connecting a plurality of electrodes formed on one main surface of the semiconductor chip and the plurality of electrode members respectively, a step of forming a resin encapsulater for sealing the semiconductor chip and the plurality of electrode members on the one main surface of the substrate, and a step of separating the semiconductor chip and the plurality of electrode members from the substrate together with the resin encapsulater.Type: GrantFiled: July 24, 2001Date of Patent: January 4, 2005Assignee: Renesas Technology CorporationInventors: Tadatoshi Danno, Katsuo Arai, Ichio Shimizu
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Patent number: 6474987Abstract: A wafer (22) is placed on an upper surface of a holder body (23), and the holder body is inserted into a plurality of holder-aimed concave recesses (14) formed on supporters (12) accommodated in a heat treatment furnace such that the holder body is held horizontally. The holder body is formed into a disk shape free of recessed cut portions, and the holder body is formed with an upwardly projecting ring-like projection (24) extending in the circumferential direction of the holder body around the axis of the holder body. The wafer holder is constituted such that the wafer is placed on the holder body while contacting with the upper surface of the projection, and such that the outer diameter of the projection is formed to be in a range of 0.5D to 0.98D wherein D is the diameter of the wafer, so that the outer periphery of the wafer is kept from contacting with the projection. Occurrence of slips in the wafer is restricted by preventing warpage of the holder body upon fabricating the holder body.Type: GrantFiled: July 9, 2001Date of Patent: November 5, 2002Assignees: Mitsubishi Materials Silicon Corporation, Mitsu Engineering & Ship Building Co., Ltd., Shinku Giken Co., Ltd.Inventors: Tetsuya Nakai, Katsuo Arai, Makoto Shinohara, Fumitomo Kawahara, Makoto Saito, Yasuhiko Kawamura
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Publication number: 20020025607Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a substrate in which a plurality of electrode members are individually placed on one main surface thereof in separated form, a step of placing a semiconductor chip on the one main surface of the substrate and electrically connecting a plurality of electrodes formed on one main surface of the semiconductor chip and the plurality of electrode members respectively, a step of forming a resin encapsulater for sealing the semiconductor chip and the plurality of electrode members on the one main surface of the substrate, and a step of separating the semiconductor chip and the plurality of electrode members from the substrate together with the resin encapsulater.Type: ApplicationFiled: July 24, 2001Publication date: February 28, 2002Inventors: Tadatoshi Danno, Katsuo Arai, Ichio Shimizu
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Patent number: 5304512Abstract: A chip 12 having an electric circuit and a plurality of leads 8 connected electrically with the chip 12 are molded in a resin-sealed package 46 by a molding material containing a main component of a resin, by introducing a molding compound sheet 20 into the cavities 33 of molds 31, 32 before the molds are clamped, by melting the molding compound sheet 20 in the cavities 33 into a liquid molding material 45 after the mold clamping action to pressure fill up the inside of the cavities 33, and by setting the liquid molding material 45 integrally.Type: GrantFiled: December 22, 1992Date of Patent: April 19, 1994Assignee: Hitachi, Ltd.Inventors: Katsuo Arai, Sumio Okada, Takashi Ooba, Kazuya Takahashi, Mayumi Kaneko
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Patent number: 4698904Abstract: An apparatus for producing various heat exchangers is disclosed in which a plurality of heat exchangers disposed side by side are formed at once. A series of manufacturing stations for working heat exchanger components such as fins and tubes and for opening the tubes are arranged in an endless manner to thereby automatically carry out the production steps with a high productivity while meeting various requirements of the specifications of the heat exchangers with a high flexibility.Type: GrantFiled: August 20, 1986Date of Patent: October 13, 1987Assignee: Hitachi, Ltd.Inventors: Yoshio Nozawa, Izumi Ochiai, Yukio Kitayama, Masahiro Miyagi, Katsuharu Uehara, Takahiko Deguchi, Keikichi Morita, Katsuo Arai, Tamotsu Nakayama