Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

Abstract: Memory cells are disclosed comprising volatile and non-volatile portions, where the non-volatile portions provide storage of multiple non-volatile data states or bits per memory cell. Methods are provided for reading non-volatile data states from a non-volatile portion of a memory cell into a volatile portion.

Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

Abstract: A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a data buffer, and a sense amplifier between several segments of an array of FeRAM memory cells associated with a plurality of plate lines and/or word lines of the array. Various combinations of segmented bit lines, segmented plate lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

Abstract: Memory devices and methods are presented for selectively reading or writing rows or columns of memory cells in a ferroelectric memory array, wherein sense amps are selectively coupled with row lines or column lines and decoder outputs are coupled with column lines or row lines for row or column memory access operations, respectively.

Abstract: Memory cells are disclosed comprising volatile and non-volatile portions, where the non-volatile portions provide storage of multiple non-volatile data states or bits per memory cell. Methods are provided for reading non-volatile data states from a non-volatile portion of a memory cell into a volatile portion.

Abstract: A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.

Abstract: Memory devices and methods are disclosed for selectively reading or writing rows or columns of memory cells in a ferroelectric memory array, wherein sense amps are selectively coupled with row lines or column lines and decoder outputs are coupled with column lines or row lines for row or column memory access operations, respectively.

Abstract: Memory apparatus and methods are provided for storing data in a semiconductor device, comprising volatile and non-volatile portions, where the non-volatile portion comprises two ferroelectric capacitors coupled with one of two internal nodes in the volatile memory portion. Apparatus is also disclosed wherein first and second ferroelectric capacitors are coupled with the first internal node of the volatile portion, and third and fourth ferroelectric capacitors are coupled with the second internal node of the volatile portion.

Abstract: A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a data buffer, and a sense amplifier between several segments of an array of FeRAM memory cells associated with a plurality of plate lines and/or word lines of the array. Various combinations of segmented bit lines, segmented plate lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

Abstract: A light-sensing diode in a high resistivity semiconductor substrate of a first conductivity type, the substrate having a surface protected by an insulator, comprising

Abstract: Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline. The cells individually comprise a transistor and an FE capacitor where a single cell within the group or array is connected to a bitline for external access during read, write, and/or restore operations. Methods are also disclosed for reading target cells in a memory cell group.

Abstract: A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.

Abstract: Memory devices and methods are disclosed for reading a restoring data from and to ferroelectric memory cells, wherein a data bit is sensed from a data memory cell, a toggle bit is sensed from a toggle memory cell, and the sensed data bit is transferred to an IO line in either inverted form or non-inverted form according to the sensed toggle bit. The sensed data bit and the toggle bit are then inverted and restored to the data and toggle memory cells so as to mitigate or reduce cell imprint.

Abstract: A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a sense amplifier, a data buffer, and a dummy cell between several segments of an array of FeRAM memory cells associated with a pair of bitlines of the array. Various combinations of segmented bit lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.

Abstract: A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

Abstract: A light-sensing diode fabricated in a semiconductor substrate having a surface protected by an insulator, comprising a first region of one conductivity type in this substrate, a second region of the opposite conductivity type forming a junction with the first region in the substrate; this junction having a convoluted shape, providing two portions generally parallel to the surface, and a constricted intersection with the surface; and a gate for applying electrical bias across the junction, this gate positioned on the insulator such that it covers all portions of the junction intersection with the surface, thereby creating a gate-controlled photodiode.

Abstract: A light-sensing diode in a high resistivity semiconductor substrate of a first conductivity type, the substrate having a surface protected by an insulator, comprising

Abstract: A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction formed by p-well and n-well regions, and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor. In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.