Abstract: An object of the present invention is to provide a prober that is able to carry out accurate inspection of semiconductor device in wafer state by reducing the effect of the external noises and the leakage of current and further by eliminating the stray capacitance of the chuck stage against the prober housing.

Abstract: An object of the present invention is to provide a prober that is able to carry out accurate inspection of semiconductor device in wafer state by reducing the effect of the external noises and the leakage of current and further by eliminating the stray capacitance of the chuck stage against the prober housing.

Abstract: A probe assembly for inspecting power semiconductor devices, which includes a probe block having more than one probe holding hole, more than one probe, each of which is contained in one of the probe holding holes with its outer surface being in contact with the inner surface of the probe holding hole, and which has lower end protruding from the probe block and coming into contact with the power semiconductor device on inspection, and one or more cooling units which cool the probe block. According to the probe assembly and the inspection apparatus, it is possible to inspect characteristics of power semiconductor devices accurately by suppressing temperature rises of the probes as well as the power semiconductor device under test.

Abstract: A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip stack device testing method testing a chip stack device configured by stacking a plurality of chips separated by dicing a substrate under test tested in a testing unit. A tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test is used, one or a plurality of the chip stack devices are attached and supported to an adhesive layer of the tray for chip stack devices to align the chip stack devices with positions of the respective chips of the undiced substrate under test, the tray for chip stack devices is installed in the testing unit in a similar manner to that in a test of the substrate under test, and the respective chip stack devices are tested.

Abstract: An inspection apparatus is provided, which includes probes for front side electrodes, probes for back side electrodes, and a chuck stage. The probes for front side electrodes and the probes for back side electrodes are formed on the upper surface of the chuck stage, and the probe contact area electrically continues to the wafer holding area, and the probes for front side electrodes and the probes for back side electrodes are located leaving a distance in horizontal direction between them so that the probes for back side electrodes move relatively within the probe contact area when the probes for front side electrodes are moved relatively within the wafer under test by the movement of the chuck stage.

Abstract: A wafer prober is provided with a tray which supports a wafer at a set position, transports it to a processing position of the wafer and is placed at the processing position; one or more alignment units which position the wafer at the set position with respect to the tray; contact units arranged in number larger than that of the alignment units and performing inspection processing in contact with the wafer at the processing position; and a tray transport portion for transporting the tray supporting the wafer between the alignment unit and the contact unit. The tray is provided with three or more pin holes for allowing movement of the chuck pin in the XYZ? directions, an alignment mark for positioning the wafer, and an alignment portion for positioning the tray itself.

Abstract: The inspection apparatus includes a probe having a contact for contacting an electrode of an inspected object and having a built-in heater for correcting dislocation of the contact to the electrode caused by temperature difference between the probe and the inspected object; a tester for testing the probe and supplying electric power to the heater; an electric power supply, provided on the tester, for supplying electric power to the heater; and a temperature control unit for controlling electric power to the heater of the probe through the electric power supply, wherein the electric power supply includes at least one open/close switch for switching power to the heater on and off. A connector has a male connector and a female connector on opposing ends. A continuity-checking device checks supply of electric power to the heater from the electric power supply.

Abstract: A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip stack device testing method testing a chip stack device configured by stacking a plurality of chips separated by dicing a substrate under test tested in a testing unit. A tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test is used, one or a plurality of the chip stack devices are attached and supported to an adhesive layer of the tray for chip stack devices to align the chip stack devices with positions of the respective chips of the undiced substrate under test, the tray for chip stack devices is installed in the testing unit in a similar manner to that in a test of the substrate under test, and the respective chip stack devices are tested.

Abstract: A wafer prober is provided with a tray which supports a wafer at a set position, transports it to a processing position of the wafer and is placed at the processing position; one or more alignment units which position the wafer at the set position with respect to the tray; contact units arranged in number larger than that of the alignment units and performing inspection processing in contact with the wafer at the processing position; and a tray transport portion for transporting the tray supporting the wafer between the alignment unit and the contact unit. The tray is provided with three or more pin holes for allowing movement of the chuck pin in the XYZ? directions, an alignment mark for positioning the wafer, and an alignment portion for positioning the tray itself.

Abstract: An inspection apparatus is provided to perform an accurate temperature control, cut a noise wave, overcome contact failure, and improve inspection accuracy. The inspection apparatus includes a probe device having a contact for contacting with an electrode of an inspected object and having a built-in heater for correcting dislocation of the contact to the electrode caused by temperature difference between the probe device and the inspected object; a tester for testing probe device and supplying electric power to the heater; an electric power supply system, provided on the tester, for supplying electric power to the heater; and a temperature control unit for controlling electric power to the heater of the probe device through the electric power supply system, wherein the electric power supply system includes at least one open/close switch for switching on and off power supply to the heater. A connector including a male connector and a female connector provided on the other end are provided.

Abstract: Reliability of results of a test such as a wafer burn-in test is raised. The present invention is a method for testing a plurality of semiconductor devices in a semiconductor wafer held in a cartridge. Each of the semiconductor devices has electrodes and the cartridge has a lower cartridge portion provided with a chuck holding the semiconductor wafer thereon, and an upper cartridge portion provided with a probe assembly having probes capable of contacting said electrodes. After constituting the cartridge and before placing the cartridge in the thermostatic chamber, a contact check to determine whether or not electrical contact between the electrodes of the semiconductor devices in the cartridge and the probes of the probe assembly is appropriate is performed.

Abstract: Reliability of results of a test such as a wafer burn-in test is raised. The present invention is a method for testing a plurality of semiconductor devices in a semiconductor wafer held in a cartridge. Each of the semiconductor devices has electrodes and the cartridge has a lower cartridge portion provided with a chuck holding the semiconductor wafer thereon, and an upper cartridge portion provided with a probe assembly having probes capable of contacting said electrodes. After constituting the cartridge and before placing the cartridge in the thermostatic chamber, a contact check to determine whether or not electrical contact between the electrodes of the semiconductor devices in the cartridge and the probes of the probe assembly is appropriate is performed.