Patents by Inventor Katsuro Hirayama

Katsuro Hirayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220403524
    Abstract: A modified resin base material that includes a resin material having a base at a surface thereof, and a plating catalytic metal on the surface of the resin material, wherein a combination of the plating catalytic metal and the base is at least one of the following Lewis acid-base combinations according to a HSAB principle: a hard acid and a hard base or an intermediate base, an intermediate acid and a hard base, an intermediate base or a soft base, or a soft acid and an intermediate base or a soft base.
    Type: Application
    Filed: August 17, 2022
    Publication date: December 22, 2022
    Inventors: Tomoji OHISHI, Yasushi YOSHIDA, Katsuro HIRAYAMA
  • Patent number: 8759953
    Abstract: In an electronic component, an active chip element and a passive chip element are respectively enclosed within first and second resin layers, which are separately disposed on upper and lower surfaces of a core substrate, respectively. The first resin layer includes a shielding metal film disposed on an upper surface thereof and a first via-hole conductor which connects the shielding metal film with a circuit pattern provided on the core substrate. The second resin layer includes an external-terminal electrode disposed on a lower surface thereof and a second via-hole conductor which connects the external-terminal electrode with a circuit pattern provided on the core substrate.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: June 24, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yuki Yamamoto, Jun Harada, Hiroshi Takagi, Katsuro Hirayama
  • Patent number: 8069558
    Abstract: A method for manufacturing a substrate having built-in components prevents a short circuit caused by the spread of solder or conductive adhesive. Land regions to connect a circuit component and a wetting prevention region surrounding the land regions are formed on one primary surface of a metal foil. Terminal electrodes of the circuit component are electrically connected to the land regions using solder, and an uncured resin is disposed on and pressure bonded to the metal foil and the circuit component, so that a resin layer in which the circuit component is embedded is formed. Subsequently, a wiring pattern is formed by processing the metal foil. The wetting prevention region is a region obtained by roughening or oxidizing one primary surface of the metal foil so as to reduce solder wettability.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: December 6, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Katsuro Hirayama, Shigeo Nishimura
  • Publication number: 20100083495
    Abstract: A method for manufacturing a substrate having built-in components prevents a short circuit caused by the spread of solder or conductive adhesive. Land regions to connect a circuit component and a wetting prevention region surrounding the land regions are formed on one primary surface of a metal foil. Terminal electrodes of the circuit component are electrically connected to the land regions using solder, and an uncured resin is disposed on and pressure bonded to the metal foil and the circuit component, so that a resin layer in which the circuit component is embedded is formed. Subsequently, a wiring pattern is formed by processing the metal foil. The wetting prevention region is a region obtained by roughening or oxidizing one primary surface of the metal foil so as to reduce solder wettability.
    Type: Application
    Filed: December 17, 2009
    Publication date: April 8, 2010
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Katsuro HIRAYAMA, Shigeo NISHIMURA
  • Publication number: 20060267159
    Abstract: In an electronic component, an active chip element and a passive chip element are respectively enclosed within first and second resin layers, which are separately disposed on upper and lower surfaces of a core substrate, respectively. The first resin layer includes a shielding metal film disposed on an upper surface thereof and a first via-hole conductor which connects the shielding metal film with a circuit pattern provided on the core substrate. The second resin layer includes an external-terminal electrode disposed on a lower surface thereof and a second via-hole conductor which connects the external-terminal electrode with a circuit pattern provided on the core substrate.
    Type: Application
    Filed: August 2, 2006
    Publication date: November 30, 2006
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuki YAMAMOTO, Jun HARADA, Hiroshi TAKAGI, Katsuro HIRAYAMA