Abstract: In a multiprocessor system in which a plurality of instruction processors (IP's) share a main storage (MS) and a channel controller (CHC) through a system controller (SC), when an I/O interrupt request is issued, IP's connected to the SC are examined to determine whether each of the IP's is executing an instruction which permits acceptance of the I/O interrupt request during the execution of the instruction. If one of the IP's is not executing such an instruction and can accept the I/O interrupt request, that IP will be selected.

Abstract: In a lock control for a shared storage, each storage controller (SC) includes circuitry (LKA) for holding the addresses locked by any of the storage utilizing units connected thereto and circuitry (FLKA) for holding a copy of the contents of LKAs of the other SCs. When one storage utilizing unit connected to one SC issues a storage access request, its requested address is compared with the contents of the LKA and FLKA in the associated SC, thus determining whether or not the requested address is locked by any other storage utilizing unit connected to that particular SC or by any of the storage utilizing units connected to the other SCs. Each storage utilizing unit may include a FLKA.

Abstract: An access control system for controlling the access to a storage which is divided into a hardware area inaccessible to ordinary programs and a software area for storing the ordinary programs, includes an address registration device and access controller. The address registration device has a plurality of entries, each of which holds a previously-used address of the storage and a flag for indicating whether the previously-used address is included in the hardware area or not. Further, the address registration device indicates whether an address at which the storage is to be accessed, is present in the address registration device or not. The access controller controls the access to the storage in accordance with the flag from the address registration device, a signal indicative of whether the to-be-accessed address of the storage is present in the address registration device or not, and the access mode which is now used.

Abstract: A scan control apparatus performs data scan-in operation to data storage elements each constituting a bit of data unit. Data of the plural data storage elements designated by scan address are read out into a register where the data at the bit position designated by the scan address is replaced by data to be scanned-in. Subsequently, the plurality of the data storage elements are reset simultaneously to thereby set the data in the register to the original data storage elements.

Abstract: A scanning control apparatus operates to scan-in arbitrary data to data storage elements such as registers, flip-flops and memory devices in an information processing system, and also scan-out data held in the data storage elements. The data storage elements are provided with physical scanning addresses determined in accordance with the arrangement of packaging, and further provided with logical scanning addresses. In the scanning operation for storage elements, a logical scanning address is given, and the scanning control apparatus transforms the logical scanning address into physical scanning addresses, by which storage elements rendered scan-in or scan-out are selected.

Abstract: A data processing system having a main storage, a buffer storage and a control unit for controlling read and write operations of the main storage and the buffer storage is disclosed. When a data requested by a basic processing unit is not in the buffer storage, a block of data is transferred from the main storage to the control unit in a plurality of times each together with a first access request in order to write the block of data from the main storage in the buffer storage. The basic processing unit issues a second access request to the control unit to read or write data from or in the buffer storage. The control unit accepts the second request between the sequential first access requests.

Abstract: An information processing system and a logout process therefor wherein when an error takes place in a storage control unit the storage control unit is inhibited from receiving storage access requests from other processing units such as basic processing unit and I/O processing unit and the error is reported to a maintenance control unit, the said other processing units are inhibited from performing time-out detecting operation, internal information of the storage control unit at the time when the error takes place is fetched therefrom and stored in the maintenance control unit, then the inhibition of the storage access request reception and the inhibition of the time-out detecting operation are removed, and the internal information is transferred from the maintenance control unit to a certain memory for later analysis of the error.

Abstract: A stage tracer comprising a plurality of tracing units which are physically independent of one another and each of which includes a memory unit and the associated read/write control logic unit, and a common control unit provided physically independent of and electrically connected with the tracing units, to supply desired control signals to the respective read/write control logic units. In each tracing unit, under the control of the common control unit, the read/write control logic unit causes the signals to be observed to be written in the memory unit and also causes the content of the memory unit to be read out onto the data bus common with all the tracing units.

Abstract: In a system which employs SEC-DED codes constituted by data bits added to redundant bits and is capable of detecting and correcting a single bit error while detecting a double or more bit error, detection is made on miscorrection ascribable to a triple bit error. When a single bit error is detected by an error detecting and correcting circuit in the SEC-DED code read out from a memory, all the corrected data bits are inverted in state and rewritten in the memory after having been added to new redundant bits. Subsequently, the data bits together with the redundant bits are read out from the memory and supplied to the error detecting and correcting circuit. The data bits obtained from the error detecting and correcting circuit are compared with the corrected and inverted data bits available before being written in the memory, to thereby determine the presence of an error encompassing more than (m+1) bits on the basis of the result of comparison.