Abstract: One end of each of five resistors is connected to each of the two ends and the respective intermediate points of a cascade of four depression-type FETs, while the other ends of the five resistors are provided with a predetermined voltage. This configuration fixes the source-drain potential of the four FETs. This fixing of the source-drain potential of the FETs permits stable application of a bias voltage for turning ON the FETs between the gate and the source each FET, so as to ensure the ON-OFF switching of the FETs.

Abstract: A high-frequency circuit is provided that can prevent the generation of an undesired peak and contribute to the reduction in area of a chip. The high-frequency circuit includes an amplifying block 10 in which an amplifying element 11, a choke inductor 12, and a by-pass capacitor 13 are provided, and an amplifying block 20 in which an amplifying element 21, a choke inductor 22, and a by-pass capacitor 23 are provided. Electric power is supplied from a common power terminal 31 to the amplifying element 21 via the choke inductor 22 and to the amplifying element 11 via the choke inductor 12 and a resistive element 37. The amplifying elements 11 and 21, the choke inductors 12 and 22, the by-pass capacitors 13 and 23, and the resistive element 37 are formed on the same substrate.

Abstract: The invention is directed to the provision of a two-input, four-output high frequency switch circuit that can prevent the occurrence of in-band ripples of insertion loss in an ON path. The high frequency switch circuit is constructed from six field effect transistors, and a signal is passed through a selected one of signal paths in the two-input, four-output high frequency signal switch having a total of six signal terminals, wherein four additional field effect transistors, each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of an external circuit, are respectively connected between ground and the signal paths leading to the remaining four signal terminals to which the signal is not passed and which therefore become open ends.

Abstract: A high-frequency circuit is provided that can prevent the generation of an undesired peak and contribute to the reduction in area of a chip. The high-frequency circuit includes an amplifying block 10 in which an amplifying element 11, a choke inductor 12, and a by-pass capacitor 13 are provided, and an amplifying block 20 in which an amplifying element 21, a choke inductor 22, and a by-pass capacitor 23 are provided. Electric power is supplied from a common power terminal 31 to the amplifying element 21 via the choke inductor 22 and to the amplifying element 11 via the choke inductor 12 and a resistive element 37. The amplifying elements 11 and 21, the choke inductors 12 and 22, the by-pass capacitors 13 and 23, and the resistive element 37 are formed on the same substrate.

Abstract: The present invention includes a die pad; signal leads, ground connection leads connected to the die pad; a semiconductor chip including electrode pads for grounding; metal thin wires, and an encapsulating resin for encapsulating the die pad and the semiconductor chip and encapsulating the signal leads and the ground connection lead such that lower portions of the signal leads and the ground connection lead are exposed as external terminals. The ground connection lead is connected to the electrode pad for grounding, so that the resin-encapsulated semiconductor device is electrically stabilized. Furthermore, interference between high frequency signals passing through the signal leads can be suppressed by the die pad and the ground connection leads.

Abstract: In order that the DC potential of the input terminal does not rise, whereby ON/OFF switching is accordingly performed normally, even when a signal having a large amplitude is inputted to an input terminal, thereby the depletion layer expands due to electron trapping effect, a first field effect transistor is connected between a first switch input terminal and a first switch output terminal in a manner that the source is arranged on the first switch input terminal side, a second field effect transistor is connected between the first switch output terminal and a second switch input terminal in a manner that the source is arranged on the second switch input terminal side, a third field effect transistor is connected between the second switch input terminal and a second switch output terminal in a manner that the source is arranged on the second switch input terminal side, and a fourth field effect transistor is connected between the second switch output terminal and the first switch input terminal in a manner th

Abstract: The present invention provides a frequency conversion circuit capable of reducing current without impairing high frequency characteristics. A local oscillator amplifier is formed of a first field effect transistor. A source thereof is grounded by a first capacitor in terms of high frequency, and a gate thereof is connected to one end of each of first and second resistors. The other end of the first resistor is grounded, and the other end of the second resistor is connected to a voltage supply terminal. An intermediate frequency amplifier is formed of a second field effect transistor. A source thereof is grounded through a third resistor and a second capacitor that are connected in parallel with each other. A drain thereof is connected to an intermediate frequency signal output terminal through a third capacitor and an intermediate frequency output matching circuit. The source of the first field effect transistor and the drain of the second field effect transistor are connected through an AC blocking circuit.

Abstract: The invention is directed to the provision of a two-input, four-output high frequency switch circuit that can prevent the occurrence of in-band ripples of insertion loss in an ON path. The high frequency switch circuit is constructed from six field effect transistors, and a signal is passed through a selected one of signal paths in the two-input, four-output high frequency signal switch having a total of six signal terminals, wherein four additional field effect transistors, each of which, when ON, provides a characteristic impedance matched to the characteristic impedance of an external circuit, are respectively connected between ground and the signal paths leading to the remaining four signal terminals to which the signal is not passed and which therefore become open ends.

Abstract: To achieve linear gain control (with a flatness of ±1 dB) over a wide range of 70 dB or greater using a single control voltage, an attenuator of the following configuration is provided in a radio frequency section of a transmitter of a cellular mobile telephone terminal. That is, a signal inputpart (34) and signal output part (35) for a radio frequency signal are connected by a signal line (51) containing at least two series variable resistors (51 and 52); parallel variable resistors (53 and 54) are connected between a ground line (57) and the signal inputpart (34) and signal outputpart (35), respectively; a gain control line (56) is connected to the variable resistors (51, 52, 53, and 54); reference voltage application parts (23, 27, 31, and 33) are connected to the variable resistors (51, 52, 53, and 54), respectively; and a gain control voltage application part (19) is connected to each of the variable resistors (51, 52, 53, and 54) via the gain control line (56).

Abstract: To achieve linear gain control (with a flatness of ±1 dB) over a wide range of 70 dB or greater using a single control voltage in a high frequency section of a mobile terminal transmitter, a signal input part 34 and a signal output part 35 are connected by a signal line 51 containing at least two series variable resistors 51 and 52, parallel variable resistors 53 and 54 are connected between a ground line 57 and the signal input part 34 and signal output part 35, respectively, a gain control line 56 is connected to the variable resistors 51, 52, 53, and 54, reference voltage application parts 23, 27, 31, and 33 are connected to the variable resistors 51, 52, 53, and 54, respectively, and a gain control voltage application part 19 is connected to the variable resistors 51, 52, 53, and 54 via the gain control line 56.

Abstract: The semiconductor device of the invention includes: a square die pad, to which a semiconductor chip is adhered via a silver paste member or the like; first leads, the inner end of each of the first leads being formed continuously and integrally with an associated shorter side of the die pad; and a pair of second leads extending in an outer direction, the inner ends of the second leads interposing the die pad therebetween. The inner end of each of the second leads includes a width-increased end portion having a larger width and being formed to be parallel to an associated longer side of the die pad. A through hole is provided in a portion connecting the width-increased end portion to the outer portion of each of the second leads. The semiconductor chip is electrically connected to the second leads via wires and to the die pad via a grounding wire.

Abstract: The present invention relates to an amplifier having high amplification efficiency. Amplification efficiency at low output is improved by reducing current at a latter stage depending on output power at the time when output power is reduced by gain control. In order to accomplish this improvement, gain control voltage applied to a gain control circuit for controlling the gain of a signal-amplifying field-effect transistor in a former stage is also applied simultaneously to a bias voltage control circuit for controlling the voltage between the gate and source of a signal-amplifying field-effect transistor in the latter stage, the voltage between the gate and source of the signal-amplifying field-effect transistor in the latter stage is controlled depending on the gain of the signal-amplifying field-effect transistor in the former stage to control the current between the drain and source of the signal-amplifying field-effect transistor in the latter stage.

Abstract: This invention relates to a method of manufacturing an Arsenic-including compound semiconductor device comprising the steps of forming an ion implantation layer in a specified region of an As compound semiconductor wafer, forming an As layer on the surface of the wafer, and annealing the water. In this manner, As evaporation in the ion implantation layer by annealing heat may be prevented. Accordingly, sufficient substitution of the implanted ions and the ions other than As ions composing the As compound may be achieved, thereby preventing lowering of the electrical activation of the As compound semiconductor device. In addition, the electrical activation becomes uniform over the whole area of the water.