Patents by Inventor Katsutomi Harada

Katsutomi Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Charge extraction circuit for voltage converter
    Patent number: 9166476
    Abstract: A power supply circuit that includes a voltage conversion circuit (CONV) for outputting an output voltage to an output voltage terminal, the output voltage being stepped up or stepped down from an input voltage (VIN) presented to an input voltage terminal, an output capacitor (COUT) coupled to the output voltage terminal, and a charge extraction circuit for extracting the charge of the output capacitor (COUT). Quick response to overshoot of VOUT generated by a sudden reduction in load current (ILOAD) is afforded, and overshoot is minimized.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: October 20, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Katsutomi Harada
  • Power Supply Circuit
    Publication number: 20130162235
    Abstract: A power supply circuit that includes a voltage conversion circuit (CONY) for outputting an output voltage to an output voltage terminal, the output voltage being stepped up or stepped down from an input voltage (VIN) presented to an input voltage terminal, an output capacitor (COUT) coupled to the output voltage terminal, and a charge extraction circuit for extracting the charge of the output capacitor (COUT). Quick response to overshoot of VOUT generated by a sudden reduction in load current (ILOAD) is afforded, and overshoot is minimized.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Inventor: Katsutomi Harada
  • Current source circuit
    Patent number: 6320364
    Abstract: A start signal is supplied to MOS transistor Q8, MOS transistor Q8 is turned on, the first current mirror circuit is driven, and the same mirror current flows in MOS transistors Q4-Q7. Then, of two MOS transistors Q8 and Q9 that compose the second current mirror circuit, to MOS transistor Q8 is connected a resistor R2 and to MOS transistor Q9 is supplied a reference signal (Vref). According to such a configuration, reference current (Iref) that is generated in resistor R2 becomes current corresponding to the reference signal (Vref), and thereby output current (Iout) is outputted from MOS transistor Q7 based on this reference current (Iref).
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: November 20, 2001
    Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
    Inventors: Tetsuo Tateishi, Katsutomi Harada