Abstract: A two-wire fire sensing and receiving system having a plurality of fire sensors connected in parallel in which;the difference in current level between a feeding electric current of a relatively small level for controlling the system and a sensing current of a relatively high level for causing the switching element of an alarm device to be conductive is reliably maintained to distinguish their current levels by restraining the current which tends to increase at the beginning of capacitor charging and at intermittent charging periods within the level of the feeding electric current without being affected by the fluctuation in power supply voltage.

Abstract: In a thyristor fire-responsive control device including a fire detector which has a thyristor as output switching means, a control circuit is responsive to the detector. A controlled apparatus is responsive to the detector through the control circuit for fire preventing operation thereof. A oscillator is connected to periodically reset the thyristor of the detector. Delay means is connected to continue the energization of the controlled apparatus for a predetermined interval after each transient resetting of the thyristor so that said controlled apparatus can operate continuously only during an interval in which the detector persists in its detecting operation.

Abstract: Disclosed is a two-wire system including a power source, a signal receiving section and a sensing device in series which supplies electric power to and receives sensing signals from signaling devices in the system. A capacitor is connected to each sensing device for preventing a voltage drop upon initiation of its sensing action. A buffer circuit is further coupled with the receiving section for protecting against false operation by an initial current which increases upon switching on the power source, thus ensuring the system becomes stable.

Abstract: An oscillator circuit comprised of three bistable circuits connected in cascade, a circuit for generating first timing signals, and a circuit for generating second timing signals. Output signals from the series of bistable circuits are applied to enable the circuits for generating timing signals, and the timing signals are applied to an input of the series of bistable circuits to change the states of the bistable circuits. After a first time interval has elapsed the first timing signal changes the state of a first bistable circuit which in turn successively changes the states of the other bistable circuits. After a second time interval has elapsed after the changes of state effectuated by the first timing signal, the second timing signal changes the state of the first bistable circuit which in turn successively changes the states of the other bistable circuits, so that the bistable circuits repetitively change state with a period equal to the sum of the first and the second time intervals.