Abstract: According to one embodiment, there is provided a motor control device including an acquisition unit, an AD conversion unit, a calculation unit and a drive control unit. The acquisition unit acquires an analog signal indicating a rotational position of a motor. The AD conversion unit AD-converts the analog signal to generate a digital value. The calculation unit estimates a slope of a waveform of the analog signal by using a plurality of the digital values and obtains an intersection timing at which a straight line corresponding to the estimated slope intersects with a threshold. The drive control unit controls driving of the motor according to a rotation cycle obtained from a plurality of the intersection timings.

Abstract: According to one embodiment, there is provided a control device including a determination unit, a correction unit and a drive controller. The determination unit determines whether a phase of a rotor of a stepping motor is ahead of or behind a target phase. The correction unit selects a correction value for a control value of a drive current of the stepping motor from among a plurality of correction values based on a determination result. The drive controller corrects the control value of the drive current with the selected correction value to drive the stepping motor.

Abstract: According to one embodiment, there is provided a motor control device including an acquisition unit, an AD conversion unit, a calculation unit and a drive control unit. The acquisition unit acquires an analog signal indicating a rotational position of a motor. The AD conversion unit AD-converts the analog signal to generate a digital value. The calculation unit estimates a slope of a waveform of the analog signal by using a plurality of the digital values and obtains an intersection timing at which a straight line corresponding to the estimated slope intersects with a threshold. The drive control unit controls driving of the motor according to a rotation cycle obtained from a plurality of the intersection timings.

Abstract: According to one embodiment, there is provided a control device including a determination unit, a correction unit and a drive controller. The determination unit determines whether a phase of a rotor of a stepping motor is ahead of or behind a target phase. The correction unit selects a correction value for a control value of a drive current of the stepping motor from among a plurality of correction values based on a determination result. The drive controller corrects the control value of the drive current with the selected correction value to drive the stepping motor.

Abstract: A display memory able to reduce power consumption, able to generate graphics at a high speed, and not needing memory mapping, a driver circuit, a display using the driver circuit, and a portable information apparatus, wherein a CPU read circuit is connected to one bit line of a display memory 7, a display read circuit is connected to the other bit line, a write circuit is connected to both bit lines, the CPU read circuit and write circuit are assigned to the access from the CPU, the display read circuit is assigned to the display screen display, and further the access from the CPU and the reading to the display screen are assigned to different two level periods of a clock signal of the memory and independently controlled. Further, a drive power supply of the display memory is divided and a drive power supply voltage is supplied to the display memory for every memory cell or for every plurality of memory cells.

Abstract: An error correction device for an optical disk reproduction unit for reproducing recorded information from an optical disk recorded with a code row data added with an error code in the same direction as a sequence of recorded information in the recording portion of the optical disk, and recorded guide information recorded in an inerasable state as a guide for recording the code row data before the code row data is recorded, wherein a prepit decoder as a first position detection portion is configured to detect a physical configurational singular point in the recorded guide information as a first position, a second position generating portion is configured to generate a second position replacing the first position detected by the prepit decoder with the code row data position, and an error correction circuit is configured to erase-correct error in the code row data using the second position.

Abstract: It is a task to provide a magnetic storage device of complementary type, of which reliability is improved by precisely performing writing storage data. In the present invention, therefore, in a magnetic storage device of complementary type for storing storage data contrary to each other in a first ferromagnetic tunnel junction element and a second ferromagnetic tunnel junction element, respectively, the first ferromagnetic tunnel junction element and the second ferromagnetic tunnel junction element are formed adjacently on a semiconductor substrate, first writing lines is wound around the first ferromagnetic tunnel junction element like a coil and the same time second writing lines is wound around the second ferromagnetic tunnel junction element like a coil, and in addition, a winding direction of the first writing lines and a winding direction of the second writing lines are reversed to each other.

Abstract: The object of the present invention is to provide a composite storage circuit capable of executing a writing operation and reading operation at high speed, and as the result of that, a semiconductor apparatus capable of realizing an instant-on function and an instant-off function is provided. The composite storage circuit is constituted of a volatile storage circuit and a non-volatile storage circuit connected in parallel, and the same information as storage information in the volatile storage circuit is stored in the non-volatile storage circuit. Moreover, as a power supply to the volatile storage circuit decreases, storage information in the volatile storage circuit is written in the non-volatile storage circuit. Further, after a power failure or a decreased power supply, storage information from the non-volatile storage circuit is returned to the volatile storage circuit upon restarting power feeding. Further, a semiconductor apparatus is constituted by having the composite storage circuit described above.

Abstract: It is an object to provide, in a data storage circuit for storing data, a power saving data storage circuit and a data writing method in the data storage circuit, and, further, to provide a data storage device. Thus, in the present invention, reading out existing data stored in a storage element M is performed prior to performing writing of new data to the storage element M to compare the existing data and the new data. The data storage circuit is configured so that in a case where the existing data and the new data are identical with each other, writing to the storage element M is not performed, and, in a case where the existing data and the new data are not identical with each other, writing of the new data to the storage element M is performed. The data storage circuit is formed on a semiconductor substrate to have a data storage device.

Abstract: A magnetic storage apparatus capable of performing storage data to a ferromagnetic tunnel junction device surely and with a low electric consumption. In the present invention, a magnetic storage apparatus using a ferromagnetic tunnel junction device configured so as to perform writing of storage data into the ferromagnetic tunnel junction device by applying writing magnetic force on the ferromagnetic tunnel junction device and to perform reading of storage data written in the ferromagnetic tunnel junction device by detecting a resistance value of the ferromagnetic tunnel junction device is provided, wherein it is configured to be able to change the magnitude of the writing magnetic force.

Abstract: A data readout circuit for reading memory data from a resistance change memory disposed at a point where a bit line and a word line intersect by setting a potential of the bit line to a predetermined bias potential and detecting a current value flowing in the resistance change memory, includes a capacitance device connected to the bit line via a switching device; and a current supply circuit connected to both ends of the switching device to provide a current to the bit line such that the potential of the bit line is equal to a potential of the capacitance device.

Abstract: A display memory able to reduce power consumption, able to generate graphics at a high speed, and not needing memory mapping, a driver circuit, a display using the driver circuit, and a portable information apparatus, wherein a CPU read circuit is connected to one bit line of a display memory 7, a display read circuit is connected to the other bit line, a write circuit is connected to both bit lines, the CPU read circuit and write circuit are assigned to the access from the CPU, the display read circuit is assigned to the display screen display, and further the access from the CPU and the reading to the display screen are assigned to different two level periods of a clock signal of the memory and independently controlled. Further, a drive power supply of the display memory is divided and a drive power supply voltage is supplied to the display memory for every memory cell or for every plurality of memory cells.

Abstract: A display memory able to reduce power consumption, able to generate graphics at a high speed, and not needing memory mapping, a driver circuit, a display using the driver circuit, and a portable information apparatus, wherein a CPU read circuit is connected to one bit line of a display memory 7, a display read circuit is connected to the other bit line, a write circuit is connected to both bit lines, the CPU read circuit and write circuit are assigned to the access from the CPU, the display read circuit is assigned to the display screen display, and further the access from the CPU and the reading to the display screen are assigned to different two level periods of a clock signal of the memory and independently controlled. Further, a drive power supply of the display memory is divided and a drive power supply voltage is supplied to the display memory for every memory cell or for every plurality of memory cells.

Abstract: An error correction device for an optical disk unit is an error correction device of the optical disk reproduction unit for reproducing recorded information from the optical disk recorded with a code row data added with an error code in the same direction as a sequence of recorded information in the recording portion of the optical disk, recorded guide information recorded in advance in an inerasable state before the code row data is recorded as recorded guide for recording the code row data in the optical disk.

Abstract: An object of the present invention is to provide a compound storage circuit that includes a storage circuit including a volatile storage circuit and a nonvolatile storage circuit connected in parallel to each other and that is arranged to be capable of an instant-on function by storing information equal to storage information stored in the volatile storage circuit into the nonvolatile storage circuit, the compound storage circuit being capable of reducing power consumption, and a semiconductor device including the compound storage circuit.

Abstract: A memory apparatus capable of accurately reading out data stored in a memory element of variable resistance. The memory apparatus using a memory element of variable resistance whose resistance is variable between a high resistance state having a higher resistance than the resistance of the reference resistance element and a low resistance state having a lower resistance than the resistance of the reference resistance element, wherein the reference circuit of the resistance element and the reference resistance element connected in series between two reference potential terminals of different potentials and the memory circuit of a series connection of the resistance element and the memory element of variable resistance with the reference circuit and the memory circuit connected in parallel with each other, and the reference resistance element is constructed to have a variable resistance.

Abstract: A magnetic storage apparatus provided using ferromagnetic tunnel junction devices is constituted by forming the ferromagnetic tunnel junction device by laminating a fixed magnetization layer and a free magnetization layer on top and back surfaces of a tunnel barrier layer, respectively, wiring word lines in the magnetization direction of the fixed magnetization layer of the ferromagnetic tunnel junction device, and wiring bit lines in the direction orthogonal to the magnetization direction of the fixed magnetization layer of the ferromagnetic tunnel junction device, wherein two different memory states can be written in the ferromagnetic tunnel junction device by inverting the direction of the current flowing through the bit lines. At the time of writing in the ferromagnetic tunnel junction device, the direction of the current flowing through the word line is inverted in the same direction as or the opposite direction to the magnetization direction of the fixed magnetization layer.

Abstract: It is a task to provide a magnetic storage device of complementary type, of which reliability is improved by precisely performing writing storage data. In the present invention, therefore, in a magnetic storage device of complementary type for storing storage data contrary to each other in a first ferromagnetic tunnel junction element and a second ferromagnetic tunnel junction element, respectively, the first ferromagnetic tunnel junction element and the second ferromagnetic tunnel junction element are formed adjacently on a semiconductor substrate, first writing lines is wound around the first ferromagnetic tunnel junction element like a coil and the same time second writing lines is wound around the second ferromagnetic tunnel junction element like a coil, and in addition, a winding direction of the first writing lines and a winding direction of the second writing lines are reversed to each other.

Abstract: It is an object to, in a data storage circuit for storing data, provide a power saving data storage circuit and a data writing method in the data storage circuit, and further, a data storage device. Thus, in the present invention, reading out of existing data stored in a storage element M is performed prior to performing writing of new data to the storage element M to compare the existing data and the new data. The data storage circuit is configured so that in a case where the existing data and the new data are identical with each other, writing to the storage element M is not performed and, in a case where the existing data and the new data are not identical with each other, writing of the new data to the storage element M is performed. The data storage circuit is formed on a semiconductor substrate to have a data storage device.

Abstract: A data readout circuit for reading memory data from a resistance change memory disposed at a point where a bit line and a word line intersect by setting a potential of the bit line to a predetermined bias potential and detecting a current value flowing in the resistance change memory, includes a capacitance device connected to the bit line via a switching device; and a current supply circuit connected to both ends of the switching device to provide a current to the bit line such that the potential of the bit line is equal to a potential of the capacitance device.