Abstract: A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other.

Abstract: A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other.

Abstract: A semiconductor device including an intermediate insulating film formed over a plurality of first conductors over a semiconductor substrate. Contact holes are formed in the intermediate insulating film over the first conductors, and contact plugs are buried in the contact holes, respectively. A plurality of second conductors are formed over the plurality of contact plugs on the intermediate insulating film, respectively, and are electrically connected to the plurality of first conductors via the contact plugs. In certain regions of the semiconductor device, the contact plugs may terminate within the intermediate insulating film, thereby electrically insulating the second conductors from the first conductors.

Abstract: A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film.

Abstract: A semiconductor memory has a gate electrode and a pair of multilayer memory elements formed on side surfaces of the gate electrode. Each multilayer memory element includes, in sequence from the gate electrode outward, a first silicon oxide layer, a charge trapping silicon nitride layer, a second silicon oxide layer, all with L-shaped cross sections, and a protective silicon nitride layer with an approximately rectangular cross section seated in the L-shape of the second silicon oxide layer. The protective silicon nitride layer protects the charge trapping silicon nitride layer from etching damage during the formation of contact holes without adding to the area occupied by the memory cell.

Abstract: A semiconductor memory device has a low-resistivity semiconductor substrate on which a higher-resistivity semiconductor layer of the same conductivity type is formed. Memory cell transistors are formed in the semiconductor layer. A diffusion region, also of the same conductivity type, is formed below the memory cell transistors. The resistivity of the diffusion region is lower than the resistivity of the semiconductor layer. In the programming of data into the memory cell transistors by hot electron injection, the diffusion region reduces the voltage drop due to current flow from the part of the semiconductor layer near the memory cell transistors into the semiconductor substrate, thereby reducing unwanted elevation of the potential of the semiconductor layer.

Abstract: A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film.

Abstract: A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film.

Abstract: A semiconductor device including an intermediate insulating film formed over a plurality of first conductors over a semiconductor substrate. Contact holes are formed in the intermediate insulating film over the first conductors, and contact plugs are buried in the contact holes, respectively. A plurality of second conductors are formed over the plurality of contact plugs on the intermediate insulating film, respectively, and are electrically connected to the plurality of first conductors via the contact plugs. In certain regions of the semiconductor device, the contact plugs may terminate within the intermediate insulating film, thereby electrically insulating the second conductors from the first conductors.

Abstract: A semiconductor device of the present invention includes a semiconductor substrate; a diffusion layer formed about a surface of the semiconductor substrate; a first conductive layer formed on the semiconductor substrate, and an insulating layer formed on the semiconductor substrate after the first conductive layer and the diffusion layer are formed, and a second conductive layer formed on the insulating layer, and a first contact formed in the insulating layer, connecting the first conductive layer to the second conductive layer, and a second contact formed in the insulating layer, connecting the first conductive layer to the diffusion layer. In addition, a part of the diffusion layer extends to a lower portion of the first contact.

Abstract: A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film.

Abstract: A semiconductor memory has a gate electrode and a pair of multilayer memory elements formed on side surfaces of the gate electrode. Each multilayer memory element includes, in sequence from the gate electrode outward, a first silicon oxide layer, a charge trapping silicon nitride layer, a second silicon oxide layer, all with L-shaped cross sections, and a protective silicon nitride layer with an approximately rectangular cross section seated in the L-shape of the second silicon oxide layer. The protective silicon nitride layer protects the charge trapping silicon nitride layer from etching damage during the formation of contact holes without adding to the area occupied by the memory cell.

Abstract: The nonvolatile semiconductor memory device includes a first conductivity-type semiconductor substrate where an active region is created, a floating gate which is formed on the first conductivity-type semiconductor substrate, and a control gate which is formed on the floating gate. A first conductivity-type high concentration diffused region is formed in the non-overlapping region of the floating gate in the active region.

Abstract: The nonvolatile semiconductor memory device 100 comprises a first conductivity-type semiconductor substrate 8 where an active region 2 is created, a floating gate 120 which is formed on the first conductivity-type semiconductor substrate, and a control gate 24 which is formed on the floating gate 120, wherein a first conductivity-type high concentration diffused region 162 is formed in the non-overlapping region with the floating gate 120 in the active region 2.