Patents by Inventor Katsutoshi Saito

Katsutoshi Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240375598
    Abstract: A wire harness including: a wire; an exterior tube that is tubular and covers an outer circumference of the wire; and a first route restrictor that is attached to an outer circumference of the exterior tube, and is configured to restrict a route of the exterior tube, wherein: the exterior tube includes a linear portion, and a corrugated portion that is continuous from the linear portion, the corrugated portion has a higher bendability than the linear portion, and the first route restrictor is attached to the corrugated portion.
    Type: Application
    Filed: December 6, 2021
    Publication date: November 14, 2024
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Katsutoshi IZAWA, Kosuke TANAKA, Ryuta SAITO
  • Publication number: 20240372345
    Abstract: A wire harness including: a wire; an exterior tube that is tubular and covers an outer circumference of the wire; and a route restrictor that is attached to an outer circumference of the exterior tube, and is configured to restrict a route of the exterior tube, wherein: the exterior tube includes a linear portion, and a corrugated portion that is continuous from the linear portion, the corrugated portion has a higher bendability than the linear portion, and the route restrictor is attached to the linear portion.
    Type: Application
    Filed: November 30, 2021
    Publication date: November 7, 2024
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Katsutoshi IZAWA, Kosuke TANAKA, Ryuta SAITO
  • Patent number: 12103476
    Abstract: A wire harness including: a wire harness body having an electric wire and a cover covering a periphery of the electric wire; a first path restrictor attached to a periphery of the cover and restricting a path of the wire harness body; and an attachment attached to a periphery of a portion of the first path restrictor in a lengthwise direction thereof.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: October 1, 2024
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Kosuke Tanaka, Ryuta Saito, Katsutoshi Izawa
  • Patent number: 12097813
    Abstract: A wire harness, including: an electric wire; and a fixing member for fixing the electric wire to an attachment object, wherein: the fixing member includes a bolt fixed portion that is fixed to a bolt included in the attachment object and a holder for holding the electric wire, the bolt fixed portion includes a fixed portion main body having an insertion hole into which the bolt is inserted and a lock ring fixed to the bolt by locking, in an axial direction, to a threaded portion of the bolt disposed in the insertion hole, the insertion hole includes a movement restrictor for restricting relative movement of the lock ring in the axial direction of the bolt, and the lock ring is configured to be movable in the insertion hole in a direction orthogonal to an axis of the bolt.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: September 24, 2024
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Ryuta Saito, Katsutoshi Izawa, Kosuke Tanaka
  • Patent number: 12043189
    Abstract: A wire harness including: a wire harness body having an electric wire and a first cover covering a periphery of the electric wire; a first path restrictor attached to a periphery of the first cover and restricting a path of the wire harness body; a second path restrictor attached to the periphery of the first cover and restricting the path of the wire harness body; and a fixing member for fixing the second path restrictor to an attachment target.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: July 23, 2024
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Ryuta Saito, Katsutoshi Izawa, Kosuke Tanaka
  • Patent number: 8137882
    Abstract: A toner for developing electrostatic images which is obtained by melt mixing at least a binder resin and a coloring agent, forming a powder material by pulverizing the obtained mixture after cooling and removing rough particles and fine particles from the formed powder material by classification, wherein inorganic fine particles having a roundness of 1.00 to 1.30, an average of the diameter of primary particles of 0.05 to 0.45 ?m and a ratio of a standard deviation to the average of the diameter of primary particles of 0.25 or smaller are added as an external additive, and a process for producing a toner for developing electrostatic images which comprises melt mixing at least a binder resin and a coloring agent, forming a powder material by pulverizing the obtained mixture after cooling, rounding the powder material by a heat treatment and adding the above inorganic fine particles to the rounded powder material.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: March 20, 2012
    Assignee: Imex Co., Ltd.
    Inventors: Shigetoshi Asano, Shuzo Nakayama, Masashi Ueda, Katsutoshi Saito, Kazuma Okamura
  • Publication number: 20100233607
    Abstract: A toner for developing electrostatic images which is obtained by melt mixing at least a binder resin and a coloring agent, forming a powder material by pulverizing the obtained mixture after cooling and removing rough particles and fine particles from the formed powder material by classification, wherein inorganic fine particles having a roundness of 1.00 to 1.30, an average of the diameter of primary particles of 0.05 to 0.45 ?m and a ratio of a standard deviation to the average of the diameter of primary particles of 0.25 or smaller are added as an external additive, and a process for producing a toner for developing electrostatic images which comprises melt mixing at least a binder resin and a coloring agent, forming a powder material by pulverizing the obtained mixture after cooling, rounding the powder material by a heat treatment and adding the above inorganic fine particles to the rounded powder material.
    Type: Application
    Filed: January 25, 2007
    Publication date: September 16, 2010
    Applicant: IMEX CO., LTD.
    Inventors: Shigetoshi Asano, Shuzo Nakayama, Masashi Ueda, Katsutoshi Saito, Kazuma Okamura
  • Patent number: 7009205
    Abstract: An image display device using transistors each having a polycrystalline semiconductor layer constructed so that drain and source regions are fully activated, and a manufacturing method thereof. The polycrystalline semiconductor layer is so provided that impurity concentrations are easy to control in LDD regions . The image display device further uses transistors having a gate electrode on an upper surface of the semiconductor layer with an insulating film therebetween, a drain region formed on one side of the gate electrode, and a source region formed on another side of the gate electrode. An activated P-type impurity is added to the area underlying the gate electrode, and an activated N-type impurity is added to the area excluding the area underlying the gate electrode.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: March 7, 2006
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Jun Gotoh, Katsutoshi Saito, Makoto Ohkura, Yukio Takasaki, Masanao Yamamoto
  • Publication number: 20030164489
    Abstract: An image display device using transistors each having a polycrystalline semiconductor layer constructed so that drain and source regions are fully activated, and a manufacturing method thereof. The polycrystalline semiconductor layer is so provided that impurity concentrations are easy to control in LDD regions . The image display device further uses transistors having a gate electrode on an upper surface of the semiconductor layer with an insulating film therebetween, a drain region formed on one side of the gate electrode, and a source region formed on another side of the gate electrode. An activated P-type impurity is added to the area underlying the gate electrode, and an activated N-type impurity is added to the area excluding the area underlying the gate electrode.
    Type: Application
    Filed: January 7, 2003
    Publication date: September 4, 2003
    Inventors: Jun Gotoh, Katsutoshi Saito, Makoto Ohkura, Yukio Takasaki, Masanao Yamamoto
  • Patent number: 6501456
    Abstract: A liquid crystal display apparatus has horizontal and vertical scanning circuits for scanning an array of pixels. An image signal applied to an image signal supply circuit in the form of series of pixel signals is transferred to pixels in the array of pixels designated by the horizontal and vertical scanning circuits. Each of the horizontal and vertical scanning circuits have a series connection of bidirectional shift register stages and are capable of bidirectional scanning. Each of the bidirectional shift register stages includes a pair of latches connected in tandem and is capable of providing an intermediate output and a shift register stage output.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: December 31, 2002
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Katsutoshi Saito, Hideo Sato, Iwao Takemoto, Katsumi Matsumoto
  • Patent number: 6373547
    Abstract: A method for forming a liquid crystal display device includes forming a metal film over a drive substrate, and patterning the metal film to form at least one pixel electrode and an optical shield film. The optical shield film is provided outside of a pixel electrode area and has a width greater than a width of each of the pixel electrode. A resin is deposited over the patterned metal film, and the resin is patterned to form at least one pole spacer and strip spacer. The strip spacer surrounds the pixel electrode area and has a width greater than a diameter of each of pole spacer. Liquid crystal material is supplied into an inside space which is surrounded by the strip spacer, and a sealing material is filled at outer edges of the strip spacer for fixing the drive substrate and a common substrate.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: April 16, 2002
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Katsutoshi Saito, Syoichi Hirota, Iwao Takemoto, Toshio Miyazawa, Katsumi Matsumoto
  • Publication number: 20010052960
    Abstract: A method for forming a liquid crystal display device includes forming a metal film over a drive substrate, and patterning the metal film to form at least one pixel electrode and an optical shield film. The optical shield film is provided outside of a pixel electrode area and has a width greater than a width of each of the pixel electrode. A resin is deposited over the patterned metal film, and the resin is patterned to form at least one pole spacer and strip spacer. The strip spacer surrounds the pixel electrode area and has a width greater than a diameter of each of pole spacer. Liquid crystal material is supplied into an inside space which is surrounded by the strip spacer, and a sealing material is filled at outer edges of the strip spacer for fixing the drive substrate and a common substrate.
    Type: Application
    Filed: July 25, 2001
    Publication date: December 20, 2001
    Inventors: Katsutoshi Saito, Syoichi Hirota, Iwao Takemoto, Toshio Miyazawa, Katsumi Matsumoto
  • Patent number: 6304308
    Abstract: Eliminating differences in cell gap of a liquid crystal panel is effected to prevent display irregularities while avoiding contamination of the liquid crystal material due to unwanted contact of a seal material with the liquid crystal material. To this end, the liquid crystal panel includes a first substrate DSUB having multiple pixel electrodes AL-P in the form of a matrix, a second substrate USUB opposing the first substrate with a specified gap therebetween and having one or more transparent electrodes ITO-C, a liquid crystal layer LC made of a liquid crystal material sealed in the gap between the opposing substrates, and an alignment film on at least one of inner surfaces of the first and second substrates in contact with the liquid crystal layer for controlling alignment of the liquid crystal material.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: October 16, 2001
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Katsutoshi Saito, Syoichi Hirota, Iwao Takemoto, Toshio Miyazawa, Katsumi Matsumoto
  • Patent number: 6232939
    Abstract: A liquid crystal display apparatus has horizontal and vertical scanning circuits for scanning an array of pixels. An image signal applied to an image signal supply circuit in the form of series of pixel signals is transferred to pixels in the array of pixels designated by the horizontal and vertical scanning circuits. Each of the horizontal and vertical scanning circuits have a series connection of bidirectional shift register stages and are capable of bidirectional scanning. Each of the bidirectional shift register stages includes a pair of latches connected in tandem and is capable of providing an intermediate output and a shift register stage output.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: May 15, 2001
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Katsutoshi Saito, Hideo Sato, Iwao Takemoto, Katsumi Matsumoto
  • Patent number: 5880795
    Abstract: A reflection-type liquid crystal display module has a liquid crystal panel including a first substrate of, for example, a rectangular shape, a second substrate opposed to the first substrate and a liquid crystal layer provided in a space between the first substrate and the second substrate to form a display screen, a package for encasing and holding the liquid crystal panel while maintaining the first substrate in an exposed state and a dichroic prism to which the first substrate is attached. At least two sides each of the first substrate have a side edge extruding outwardly over a corresponding side end of the second substrate. The side edges of the first substrate are fixed between the dichroic prism and the package, whereby the second substrate is supported by the first substrate and not by the package.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: March 9, 1999
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Tetsuya Nagata, Iwao Takemoto, Toshio Miyazawa, Katsutoshi Saito, Atsumu Iguchi
  • Patent number: 4827483
    Abstract: A semiconductor laser device including at least one of a laser active layer formed of a super lattice and an optical guide layer formed of another super lattice is disclosed in which part of at least one of the super lattices is converted into a mixed crystal by the impurity induced disordering based upon one of impurity diffusion and impurity ion implantation, to divide the super lattice into a first region formed of the mixed crystal and a second region having the super lattice structure, the width of the second region in directions perpendicular to the lengthwise direction of a laser cavity varies along the above lengthwise direction, and the width of a laser excitation region is smaller than the mean value of the width of the second region, to generate laser oscillation having a single transverse mode and a multi longitudinal mode. Thus, the semiconductor laser device emits a laser beam which is small in astigmatism and low in optical feedback noise.
    Type: Grant
    Filed: August 11, 1986
    Date of Patent: May 2, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Fukuzawa, Naoki Chinone, Shin'ichi Nakatsuka, Katsutoshi Saito, Takashi Kajimura, Yuuichi Ono
  • Patent number: 4426703
    Abstract: In a semiconductor laser device wherein a stripe-shaped impurity-diffused region is disposed in at least parts of semiconductor layers of from a surface semiconductor layer of a semiconductor layer assembly constituting the semiconductor laser device to a second semiconductor layer lying in contact with a first semiconductor layer having an active region, the impurity-diffused region having the same conductivity type as that of the second semiconductor layer and extending at least from the surface semiconductor layer to a depth vicinal to the first semiconductor layer, the impurity region serving as a current path; a semiconductor laser device characterized in that a third semiconductor layer in which the diffusion rate of an impurity for use in the formation of the impurity-diffused region is lower than in the second semiconductor layer is disposed between the surface semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: June 9, 1981
    Date of Patent: January 17, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Takao Kuroda, Takashi Kajimura, Jun-ichi Umeda, Katsutoshi Saito