Abstract: The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if the defective redundant sector signal RSECF is at a HIGH level (that is, the selected redundant sector is a defective sector), the compulsory signal FMATCH is brought to a HIGH level. The match signal MATCH is forcedly brought to a HIGH level (S22) in compliance with the compulsory signal FMATCH which is at a HIGH level (S21:T). And, verification (S2a) is skipped for the defective sectors, whereby the address signal for identifying the ordinary memory blocks may be utilized for identification of redundant memory blocks.

Abstract: When adjusting reference cells (11), the first reference unit (15) and the second reference unit (17) are used for verification operations of the reference cells (11). The first reference unit (15) provides a lower limit current of an allowable current range for currents provided from a nonvolatile transistor of the reference cells (11), and the second reference unit (17) provides an upper limit current therefor. An amplification signal REFO of the reference cells (11), which is outputted from a sense amplifier (19), is compared with amplification signals LO and HO responsive to the lower and upper limit currents outputted from sense amplifiers (21) and (23), respectively, and a verify operation is carried out to see whether or not the current provided from the nonvolatile transistor is between the lower limit current and the upper limit current of the allowable current range.

Abstract: The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if the defective redundant sector signal RSECF is at a HIGH level (that is, the selected redundant sector is a defective sector), the compulsory signal FMATCH is brought to a HIGH level. The match signal MATCH is forcedly brought to a HIGH level (S22) in compliance with the compulsory signal FMATCH which is at a HIGH level (S21:T). And, verification (S2a) is skipped for the defective sectors, whereby the address signal for identifying the ordinary memory blocks may be utilized for identification of redundant memory blocks.

Abstract: When adjusting the reference cells (11), the first reference unit (15) and the second reference unit (17) are used for a verify operation of the reference cells (11). The first reference unit (15) provides the lower limit current of the allowable current range, which is caused to flow by a nonvolatile transistor of the reference cells (11), and the second reference unit (17) provides the upper limit current thereof. An amplification signal REFO of the reference cells (11), which is outputted from a sense amplifier (19) is compared with amplification signals LO and HO responsive to the lower and upper limit currents outputted from sense amplifiers (21) and (23), and a verify operation is carried out to see whether or not the current caused to flow by the nonvolatile transistor is between the lower limit current and the upper limit current of the allowable current range.