Abstract: A microcomputer for functioning according to operation modes includes; a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.

Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Abstract: A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits a plurality of data bits represented by whether the buses be driven to the master control unit in data transmission periods assigned to the slave control units based on a start of communication, and the master control unit drives the buses to insert a period for supplying power while data bits are being transmitted in the data transmission period. The slave control unit provides a non-driving period, which stops driving the buses, at an end of the data bit transmission period.

Abstract: A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.

Abstract: A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.

Abstract: Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

Abstract: A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits a plurality of data bits represented by whether the buses be driven to the master control unit in data transmission periods assigned to the slave control units based on a start of communication, and the master control unit drives the buses to insert a period for supplying power while data bits are being transmitted in the data transmission period. The slave control unit provides a non-driving period, which stops driving the buses, at an end of the data bit transmission period.

Abstract: A reference clock oscillating circuit intermittently carries out an oscillating operation on the basis of an oscillation control signal from an oscillation control circuit. A frequency multiplying circuit successively measures the period of a reference clock signal by using a measuring clock signal generated therein during a period for which the reference clock signal is input from the reference clock oscillating circuit, and generates a multiplied clock signal by using the period data thus measured. During a period for which no reference clock signal is input, the multiplied clock signal is generated by using the period data stored in a period data register. The interval of the intermittent oscillating operation is set on the basis of temperature variation of IC or the like.

Abstract: Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.

Abstract: In a power supply circuit, when switches are turned off, current flows from a battery power supply line through resistors, input terminals, diodes and a terminal and further from a terminal into IC. When a microcomputer operates in a low power consumption operating mode, the power supply voltage is higher than a target voltage, and a control voltage output from an operational amplifier increases, so that a transistor is turned off. At this time, a current sink circuit operates and a transistor is turned on, so that excessive current flows into the current sink circuit to suppress increase of the power supply voltage.

Abstract: A reference clock oscillating circuit intermittently carries out an oscillating operation on the basis of an oscillation control signal from an oscillation control circuit. A frequency multiplying circuit successively measures the period of a reference clock signal by using a measuring clock signal generated therein during a period for which the reference clock signal is input from the reference clock oscillating circuit, and generates a multiplied clock signal by using the period data thus measured. During a period for which no reference clock signal is input, the multiplied clock signal is generated by using the period data stored in a period data register. The interval of the intermittent oscillating operation is set on the basis of temperature variation of IC or the like.