Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: An information communication terminal (100) that includes: a speech recognition module (6) for recognizing speech information to identify a plurality of words in the recognized speech information; a storage medium (20) for storing keyword extraction condition setting data (24) in which a condition for extracting a keyword is set; a keyword extraction module (8) for reading the keyword extraction condition setting data (24) to extract a plurality of keywords from the plurality of words; a related information acquisition module (11) for acquiring related information related to a plurality of keywords; and a related information output module (14) for providing related information to a monitor (2).

Abstract: An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed.

Abstract: Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

Abstract: A semiconductor integrated circuit includes an external pad, a ground line, a first protection circuit between the external pad and the ground line, and a second protection circuit between the external pad and the ground line. The second protection circuit is formed by a first protection element, a second protection element, and a resistor. With this structure, the resistance value of the resistor is set to an arbitrary value, so that an unnecessary current which would be generated at the time of power-off of the LSI can be decreased to a value which does not deteriorate the reliability of the LSI.

Abstract: A semiconductor integrated circuit includes a first functional circuit block; a second functional circuit block; a relay circuit block; a first protection circuit block; and a second protection circuit block. The first protection circuit block includes an ESD protection circuit connected between either one of a first high-voltage power supply line and a first low-voltage power supply line, and either one of a third high-voltage power supply line and a third low-voltage power supply line. The second protection circuit block includes an ESD protection circuit connected between either one of a second high-voltage power supply line and a second low-voltage power supply line, and either one of the third high-voltage power supply line and the third low-voltage power supply line.

Abstract: A semiconductor device includes a protected circuit and an electrostatic-discharge protection circuit. The electrostatic-discharge protection circuit includes a first well of a first conductivity type and a second well of a second conductivity type formed in contact with each other in a semiconductor substrate, a first impurity diffusion layer of the first conductivity type and a third impurity diffusion layer of the second conductivity type formed apart from each other in the first well, and a second impurity diffusion layer of the second conductivity type and a fourth impurity diffusion layer of the first conductivity type formed apart from each other in the second well. The second and the third impurity diffusion layers are formed adjacent to each other interposing an element isolation region provided across a border between the first and the second wells.

Abstract: The semiconductor integrated circuit device includes: a circuit to be protected connected between a power supply line and a ground line; a first resistance connected to an external input terminal at one terminal and to an input terminal of the circuit to be protected at the other terminal; a first electrostatic discharge protection circuit including a first voltage drop circuit connected to the power supply line at one terminal and to the input terminal of the circuit to be protected at the other terminal; and a second electrostatic discharge protection circuit including a second voltage drop circuit connected to the input terminal of the circuit to be protected at one terminal and to the ground line at the other terminal.

Abstract: A semiconductor integrated circuit includes: a well 35 of a first conductivity type formed on a substrate 37; a first external terminal 10, a second external terminal 11, and a third external terminal 12 provided above the substrate 37; a first protection circuit 20 provided on an electrical path between the first external terminal 10 and the second external terminal 11; a second protection circuit 21 provided on an electrical path between the second external terminal 11 and the third external terminal 12; and a third protection circuit 22 provided on an electrical path between the third external terminal 12 and the first external terminal 10. A guard ring 40 is formed continuously in the well to surround at least two circuits among the first, second, and third protection circuits 20, 21, and 22, formed on the well 35.

Abstract: A semiconductor integrated circuit includes an external pad, a ground line, a first protection circuit between the external pad and the ground line, and a second protection circuit between the external pad and the ground line. The second protection circuit is formed by a first protection element, a second protection element, and a resistor. With this structure, the resistance value of the resistor is set to an arbitrary value, so that an unnecessary current which would be generated at the time of power-off of the LSI can be decreased to a value which does not deteriorate the reliability of the LSI.

Abstract: An information communication terminal (100) that includes: a speech recognition module (6) for recognizing speech information to identify a plurality of words in the recognized speech information; a storage medium (20) for storing keyword extraction condition setting data (24) in which a condition for extracting a keyword is set; a keyword extraction module (8) for reading the keyword extraction condition setting data (24) to extract a plurality of keywords from the plurality of words; a related information acquisition module (11) for acquiring related information related to a plurality of keywords; and a related information output module (14) for providing related information to a monitor (2).

Abstract: A semiconductor integrated circuit device includes: a protected circuit protected against electro-static discharge applied from outside the device; an SCR protection circuit having an anode terminal connected to a power line, a cathode terminal connected to a ground line and a trigger terminal; and a trigger circuit connected to the trigger terminal and including an RC circuit connected between the power line and the ground line.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: Attributes of data recorded on a magnetic tape are stored in an attribute information table saved in an MIC (Memory in Cassette) of a tape cassette accommodated in a tape streamer drive connected to a host computer. The attributes are recorded for every identifier used for identifying a recording unit of the data. For each identifier, the attributes include the name of a file, a title, a file creation date/time, a file updating date/time, the amount of data contained in the file, the type of the data and a compression rate of the data. The attributes include not only those supplied by the host computer but also attributes generated after a data recording operation as information on the recording location of data. The attributes generated after the data recording operation include a group number and an offset from the beginning of the group identified by the group number. For example, the present invention can be applied to the tape streamer drive.