Abstract: When power is turned off during erasure or writing, electric charge is left due to high voltage. This charge is discharged when the power is turned on. Thus, erroneous erasure, erroneous writing, and erroneous reading are prevented. It comprises a reset circuit 2 for producing a reset signal when the power is turned on, a bias circuit 3 for producing a given voltage during the period of the reset signal, a driver 4 for selecting and driving all word lines with a given voltage during the period of the reset signal, and discharging circuits 5 for electrically discharging all control lines and all bit lines during the period of the reset signal.

Abstract: When power is turned off during erasure or writing of an EEPROM, electric charge remains on the bit and word selecting lines and on the control line due to the high voltage applied to write or erase data. This charge is discharged through the memory cells when the power is turned on. Erroneous erasure, erroneous writing, and erroneous reading are prevented by including a reset circuit for producing a reset signal when the power is turned on. A bias circuit is connected to the reset circuit for producing a predetermined voltage during the period of the reset signal. A driver circuit receptive of the reset signal selects and drives all word lines with the predetermined voltage during the period of the reset signal, and discharging circuits are provided for electrically discharging all control lines and all bit lines during the period of the reset signal. When the device is turned on, the reset signal is generated, thereby discharging the bit lines and control lines.