Patents by Inventor Katsuya Hironaka

Katsuya Hironaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory
    Patent number: 7550807
    Abstract: In the non-volatile semiconductor memory in which an N-type source diffusion layer and an N-type drain diffusion layer are formed on a P-type well formed on a substrate: the source diffusion layer has a protrusion portion and a depressed portion on a cross section taken along a plane that includes (a) a straight line extending along a direction of extension of the source diffusion layer and (b) a normal line of the semiconductor substrate, and the source diffusion layer is formed of a series of (a) an upper-wall layer constituting the protrusion portion, (b) a lower-wall layer constituting the depressed portion, and (c) a side-wall layer between the upper-wall layer and the lower-wall layer; a silicide is formed to cover the upper-wall layer, the lower-wall layer, and the side-wall layer, and an insulating layer is formed to cover the silicide; and a distance d between (a) an interface between the insulating layer and the silicide formed on the upper-wall layer and (b) an interface between the insulating laye
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: June 23, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuya Hironaka, Shinichi Sato
  • Semiconductor memory
    Publication number: 20060258108
    Abstract: In the non-volatile semiconductor memory in which an N-type source diffusion layer and an N-type drain diffusion layer are formed on a P-type well formed on a substrate: the source diffusion layer has a protrusion portion and a depressed portion on a cross section taken along a plane that includes (a) a straight line extending along a direction of extension of the source diffusion layer and (b) a normal line of the semiconductor substrate, and the source diffusion layer is formed of a series of (a) an upper-wall layer constituting the protrusion portion, (b) a lower-wall layer constituting the depressed portion, and (c) a side-wall layer between the upper-wall layer and the lower-wall layer; a silicide is formed to cover the upper-wall layer, the lower-wall layer, and the side-wall layer, and an insulating layer is formed to cover the silicide; and a distance d between (a) an interface between the insulating layer and the silicide formed on the upper-wall layer and (b) an interface between the insulating laye
    Type: Application
    Filed: May 5, 2006
    Publication date: November 16, 2006
    Inventors: Katsuya Hironaka, Shinichi Sato