Patents by Inventor Katsuya Kato
Katsuya Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240123921Abstract: Objects are: to make a fixing structure in which an engagement part of a fixing member is inserted and fixed in a through hole of a plate-shaped member, into a structure in which the fixing member is easily detached from the through hole and is less likely to be damaged or broken when being detached; and to, in doing so, maintain the dustproof and waterproof performance, the molding processability, and the elasticity of a dish-like contact portion of the fixing member at the conventional level, and suppress a size increase. To attain these objects, in a fixing structure, arc-shaped bent portions are respectively formed at both ends of a dish-like contact portion which annularly contacts a through hole surrounding portion from a near side in an insertion direction, and are guide portions for a detachment jig to enter the inside of the dish-like contact portion in the fixing structure.Type: ApplicationFiled: October 10, 2023Publication date: April 18, 2024Inventors: Toshio IWAHARA, Katsuya HIRAKAWA, Makoto KATO, Toshinori MURAMOTO
-
Publication number: 20240079341Abstract: An array of alignment marks can be formed in a substrate, and at least one material portion can be deposited and patterned. A photoresist material layer can be deposited and patterned to provide a kerf-region photoresist material portion. The overlay between the kerf-region photoresist material portion and a proximal alignment mark is measured employing a ultraviolet radiation that is focused at a focal plane located at or near a top surface of the kerf-region photoresist material portion.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventor: Katsuya KATO
-
Patent number: 11569139Abstract: A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.Type: GrantFiled: March 8, 2021Date of Patent: January 31, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Ikue Yokomizo, Michiaki Sano, Kazuto Watanabe, Hajime Yamamoto, Takashi Yamaha, Koichi Ito, Katsuya Kato, Ryo Hiramatsu, Hiroshi Sasaki, Akihiro Tobioka, Liang Li
-
Publication number: 20220285234Abstract: A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.Type: ApplicationFiled: March 8, 2021Publication date: September 8, 2022Inventors: Ikue YOKOMIZO, Michiaki SANO, Kazuto WATANABE, Hajime YAMAMOTO, Takashi YAMAHA, Koichi ITO, Katsuya KATO, Ryo HIRAMATSU, Hiroshi SASAKI, Akihiro TOBIOKA, Liang LI
-
Publication number: 20220278652Abstract: A first transistor chip (3) includes a first drain pad (5). A second transistor chip (4) includes a second drain pad (6). A transmission line (9) and a first capacitor (C1) are formed on a resin substrate (1). A first bonding wire (7) connects the first drain pad (5) and one end of the transmission line (9). A second bonding wire (10) connects the second drain pad (6) and one end of the first capacitor (C1). An output terminal (OUT) is connected to the other end of the transmission line (9) and the other end of the first capacitor (C1). A capacitance value of the first capacitor (C1) is selected so as to cause resonance with inductance of the second bonding wire (10).Type: ApplicationFiled: November 21, 2019Publication date: September 1, 2022Applicant: Mitsubishi Electric CorporationInventor: Katsuya KATO
-
Patent number: 11374539Abstract: A package (1) includes first and second input terminals (2,3) which are adjacent to each other, and first and second output terminals (4,5) which are adjacent to each other. A first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9), and a first output matching circuit (10) are sequentially connected between the first input terminal (2) and the first output terminal (4) inside the package (1). A third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14), and a third output matching circuit (15) are sequentially connected between the second input terminal (3) and the second output terminal (5) inside the package (1). First to fourth matching circuits (16-19) are respectively connected to the first input terminal (2), the second input terminal (3), the first output terminal (4) and the second output terminal (5) outside the package (1).Type: GrantFiled: August 20, 2018Date of Patent: June 28, 2022Assignee: Mitsubishi Electric CorporationInventor: Katsuya Kato
-
Publication number: 20220119498Abstract: To provide an immunoglobulin purification method which achieves a high immunoglobulin recovery percentage without causing loss of the antibody nature of an immunoglobulin. The immunoglobulin purification method includes an adsorption step and a desorption step. The adsorption step involves adsorption of an immunoglobulin onto porous zirconia particles in a neutral buffer. The desorption step involves desorption of the immunoglobulin adsorbed on the porous zirconia particles from the porous zirconia particles by means of a neutral desorption liquid.Type: ApplicationFiled: January 17, 2020Publication date: April 21, 2022Applicants: NGK Spark Plug Co., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Katsuya KATO, Fukue NAGATA, Shinjiro KASAHARA, Yuki HIROBE, Jun OTSUKA
-
Patent number: 11303254Abstract: An amplifier includes: a first transistor chip including a plurality of cells and provided beside an input matching substrate; a second transistor chip including a plurality of cells and provided beside the input matching substrate; a plurality of first bonding wires connecting the input matching substrate and the first transistor chip; and a plurality of second bonding wires connecting the input matching substrate and the second transistor chip, and variance of the mutual inductance of the first bonding wires and the second bonding wires is compensated by adjusting the self-inductance of the first bonding wires and the second bonding wires.Type: GrantFiled: May 28, 2018Date of Patent: April 12, 2022Assignee: Mitsubishi Electric CorporationInventors: Shohei Hatanaka, Katsuya Kato
-
Publication number: 20220089453Abstract: Porous zirconia particles exhibit high specificity to a protein to be immobilized thereto and are used in immobilization of the protein. The porous zirconia particles have a pore diameter D50, at which a ratio of a cumulative pore volume to a total pore volume is 50%, the pore diameter D50 being in a range of 3.20 nm or more and 6.50 nm or less; and a pore diameter D90, at which a ratio of a cumulative pore volume to a total pore volume is 90%, the pore diameter D90 being in a range of 10.50 nm or more and 100.00 nm or less. The total pore volume of the particles is greater than 0.10 cm3/g. D50, D90, and the total pore volume are determined based on a pore diameter distribution measured through a BET method.Type: ApplicationFiled: January 17, 2020Publication date: March 24, 2022Applicants: NGK Spark Plug Co., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Katsuya KATO, Fukue NAGATA, Shinjiro KASAHARA, Jun OTSUKA, Yuki HIROBE
-
Patent number: 11038612Abstract: A terminal device acquires a parameter indispensable in canceling or suppressing an interference signal, cancels or suppresses interference with high precision, and reduces a degradation in reception performance due to the interference.Type: GrantFiled: August 9, 2018Date of Patent: June 15, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Kozue Yokomakura, Ryota Yamada, Katsuya Kato, Hiromichi Tomeba
-
Patent number: 11022673Abstract: Provided is a terminal apparatus including: a receiver configured to detect a transmission direction of a signal used for communication with at least one base station apparatus; and a transmitter configured to transmit, to a location server, base station direction information for indicating the transmission direction detected.Type: GrantFiled: March 7, 2018Date of Patent: June 1, 2021Assignees: SHARP KABUSHIKI KAISHA, TOKYO INSTITUTE OF TECHNOLOGYInventors: Ryota Yamada, Katsuya Kato, Yasuhiro Hamaguchi, Kazuhiko Fukawa
-
Publication number: 20210143781Abstract: An amplifier includes: a first transistor chip including a plurality of cells and provided beside an input matching substrate; a second transistor chip including a plurality of cells and provided beside the input matching substrate; a plurality of first bonding wires connecting the input matching substrate and the first transistor chip; and a plurality of second bonding wires connecting the input matching substrate and the second transistor chip, and variance of the mutual inductance of the first bonding wires and the second bonding wires is compensated by adjusting the self-inductance of the first bonding wires and the second bonding wires.Type: ApplicationFiled: May 28, 2018Publication date: May 13, 2021Applicant: Mitsubishi Electric CorporationInventors: Shohei HATANAKA, Katsuya KATO
-
Publication number: 20210013840Abstract: A package (1) includes first and second input terminals (2,3) which are adjacent to each other, and first and second output terminals (4,5) which are adjacent to each other. A first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9), and a first output matching circuit (10) are sequentially connected between the first input terminal (2) and the first output terminal (4) inside the package (1). A third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14), and a third output matching circuit (15) are sequentially connected between the second input terminal (3) and the second output terminal (5) inside the package (1). First to fourth matching circuits (16-19) are respectively connected to the first input terminal (2), the second input terminal (3), the first output terminal (4) and the second output terminal (5) outside the package (1).Type: ApplicationFiled: August 20, 2018Publication date: January 14, 2021Applicant: Mitsubishi Electric CorporationInventor: Katsuya KATO
-
Patent number: 10869165Abstract: To provide a base station apparatus, a terminal apparatus, a location server, and a communication apparatus that are capable of improving position estimation accuracy. A physical signal generating unit configured to generate first positioning reference signal and second positioning reference signal, and a transmitter configured to transmit the first positioning reference signal and the second positioning reference signal to a terminal apparatus are provided. The first positioning reference signal is mapped on one resource block and the second positioning reference signal is mapped on at least six resource blocks. The resource block is constituted of prescribed subcarriers in a frequency domain. A maximum v number of consecutive subframes on which the first positioning reference signal is transmitted is larger than a maximum number of consecutive subframes on which the second positioning reference signal is transmitted.Type: GrantFiled: July 31, 2017Date of Patent: December 15, 2020Assignees: SHARP KABUSHIKI KAISHA, FG Innovation Company LimitedInventors: Ryota Yamada, Katsuya Kato, Yasuhiro Hamaguchi
-
Publication number: 20200329213Abstract: Provided are an image data output device, an image data output method, an image display device, and an integrated circuit that are possible to eliminate stutter by selecting a frame rate from a plurality of frame rate candidates. The image data output device that switches a frame rate of a generated image for each frame and outputs the image to an image display device includes an image generation unit that, on a basis of image generation time required to generate the image, changes the frame rate to one of a plurality of frame rates which are predetermined.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Inventors: Katsuya Kato, Hideo Namba
-
Publication number: 20200321324Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.Type: ApplicationFiled: April 2, 2019Publication date: October 8, 2020Inventors: Michiaki Sano, Takashi YAMAHA, Koichi ITO, Ikue YOKOMIZO, Ryo HIRAMATSU, Kazuto WATANABE, Katsuya KATO, Hajime YAMAMOTO, Hiroshi SASAKI
-
Patent number: 10797035Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.Type: GrantFiled: April 2, 2019Date of Patent: October 6, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Michiaki Sano, Takashi Yamaha, Koichi Ito, Ikue Yokomizo, Ryo Hiramatsu, Kazuto Watanabe, Katsuya Kato, Hajime Yamamoto, Hiroshi Sasaki
-
Patent number: 10790296Abstract: A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.Type: GrantFiled: May 21, 2019Date of Patent: September 29, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Takashi Yamaha, Katsuya Kato, Kazuto Watanabe, Hajime Yamamoto, Michiaki Sano, Koichi Ito, Ikue Yokomizo, Ryo Hiramatsu, Hiroshi Sasaki
-
Patent number: 10751289Abstract: Provided are core-shell particles which are kept stable in a solvent such as water for a long period. Each core-shell particle includes a core which contains a hydrophobic polymer having an anionic group and a shell which contains calcium phosphate. At least one of calcium atoms contained in calcium phosphate is chemically bonded to a functional group derived from the anionic group. In a method of manufacturing core-shell particles each core-shell particle includes a core which contains a hydrophobic polymer and a shell which contains calcium phosphate, the method includes the steps of: mixing a water-soluble organic solution which contains a hydrophobic polymer having an anionic group with a solution which contains calcium ion so as to obtain a first mixed solution; mixing the first mixed solution with a solution which contains phosphate ions so as to obtain a second mixed solution; and stirring the second mixed solution.Type: GrantFiled: August 31, 2015Date of Patent: August 25, 2020Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Fukue Nagata, Katsuya Kato, Masahiko Inagaki
-
Publication number: 20200216629Abstract: Provided is a composite body where ceramic crystals are thinly and uniformly coated onto a base material containing a hydrophilic polymer. The composite body has a base material containing a hydrophilic polymer, and a ceramic layer which is coated onto at least a portion of a surface of the base material, and the ceramic layer contains crystals having a laminated structure. The ceramic layer may contain calcium phosphate. A thickness of the ceramic layer is 0.3 nm to 50 nm. The composite body is produced through a step of mixing and stirring a dispersion liquid in which the base material is dispersed, a first solution containing calcium ions, and a second solution containing phosphate ions.Type: ApplicationFiled: January 29, 2018Publication date: July 9, 2020Inventors: Fukue NAGATA, Tatsuya MIYAJIMA, Katsuya KATO