Abstract: An in-vehicle acoustic system includes a first amplifier that outputs a first audio signal to a first mid-range speaker; a second amplifier that outputs a second audio signal to a second mid-range speaker; a third amplifier that outputs a third audio signal to a first high-range speaker and a first low-range speaker; and a fourth amplifier that outputs a fourth audio signal to a second high-range speaker and a second low-range speaker, in which the third audio signal is inputted to the first high-range speaker, the fourth audio signal is inputted to the second high-range speaker, the first audio signal is inputted to a deep-bass speaker, the third audio signal is inputted to the first low-range speaker, the fourth audio signal is inputted to the second low-range speaker.

Abstract: Provided are a management apparatus, a matching system, a management method, a matching method, and a storage medium that can improve matching accuracy when performing matching using passage history information. The management apparatus includes: a passenger information acquisition unit that acquires passenger information related to a passenger; and a management unit that creates matching-use passage history information used for matching based on the passenger information and passage history information related to the passenger.

Abstract: Provided are an information providing apparatus, a terminal, an identity verification system, an information providing method, and a storage medium that can perform identity verification with high usability without requiring a passenger to possess or carry a certificate or a substitute thereof. The information providing apparatus includes: a management unit that creates identity verification information on a passenger based on passage history information including biometric information on the passenger; and a transmission unit that, in response to receiving biometric information on a target person and a request for the identity verification information, transmits the identity verification information including the biometric information that matches the biometric information on the target person.

Abstract: Provided are a notification apparatus, a terminal, a notification system, a notification method, and a storage medium that can smoothly notify that a passenger is a targeted user of an automated gate. The notification apparatus includes: a determination unit that determines whether or not a passenger is a targeted user of an automated gate; and a notification unit that transmits, to a mobile terminal carried by the passenger, a notification indicating whether or not the passenger is a targeted user of the automated gate.

Abstract: A fuel vapor recovering structure for a vehicle, the vehicle having a side member extending in a longitudinal direction of the vehicle, and a cross member extending along a vehicle width direction, includes: a canister attached to the side member for absorbing a fuel evaporation gas in a fuel tank of the vehicle; and an atmosphere communicating pipe having a first end connected to the canister, and a second end opened to the atmosphere and inserted in the cross member.

Abstract: A fuel vapor recovering structure for a vehicle, the vehicle having a side member extending in a longitudinal direction of the vehicle, and a cross member extending along a vehicle width direction, includes: a canister attached to the side member for absorbing a fuel evaporation gas in a fuel tank of the vehicle; and an atmosphere communicating pipe having a first end connected to the canister, and a second end opened to the atmosphere and inserted in the cross member.

Abstract: A semiconductor laser driving circuit supplies a drive current to a semiconductor laser diode connected to an output terminal based on an input signal inputted thereto through an input terminal, thereby controlling the semiconductor laser diode. The semiconductor laser driving circuit includes a first supply portion supplying a bias current, and a first supply signal having a frequency component whose frequency is equal to or lower than a first frequency of the input signal, and a second supply portion supplying a second supply signal having a frequency component whose frequency is higher than a second frequency of the input signal.

Abstract: A semiconductor laser drive circuit controlling a semiconductor laser diode connected to an output terminal by providing a drive electric current to the semiconductor laser diode includes: a constant electric current source configured to provide an electric current to the output terminal, the constant electric current source being connected to a first electric power terminal and the output terminal; a current sinking circuit connected to the output terminal and a second electric power terminal; a current sourcing circuit configured to provide a predetermined electric current to the output terminal or the current sinking circuit, the current sourcing circuit being connected to the first electric power terminal and the output terminal; and a terminating resistor having a resistance component equal to that of the semiconductor laser diode, the terminating resistor being connected to the circuit sinking circuit and the current sourcing circuit.

Abstract: A semiconductor laser drive circuit controlling a semiconductor laser diode connected to an output terminal by providing a drive electric current to the semiconductor laser diode includes: a constant electric current source configured to provide an electric current to the output terminal, the constant electric current source being connected to a first electric power terminal and the output terminal; a current sinking circuit connected to the output terminal and a second electric power terminal; a current sourcing circuit configured to provide a predetermined electric current to the output terminal or the current sinking circuit, the current sourcing circuit being connected to the first electric power terminal and the output terminal; and a terminating resistor having a resistance component equal to that of the semiconductor laser diode, the terminating resistor being connected to the circuit sinking circuit and the current sourcing circuit.

Abstract: A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.

Abstract: A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.

Abstract: A method and apparatus are provided for a programmable impedance control circuit. In one example of the apparatus, a programmable impedance control circuit of an output driver of an input/output interface is provided. The programmable impedance control circuit includes a pull-up impedance programmed according to a multi-stage emulator and a pull-down impedance programmed according to the multi-stage emulator. The multi-stage emulator includes a first stage for calibrating a pull-up PMOS impedance at a voltage level Voh, a second stage for calibrating a pull-up NMOS impedance at a voltage level Vol, a third stage for calibrating a pull-down NMOS impedance at the voltage level Vol, a fourth stage for re-calibrating the pull-up NMOS impedance at the voltage level Vol, and fifth stage for calibrating a pull-down PMOS impedance at the voltage level Voh.

Abstract: A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, with data being continuously input or output and transferred by repeatedly executing the second processing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing, and a file storage device and a computer system util

Abstract: A method and apparatus are provided for a programmable impedance control circuit. In one example of the apparatus, a programmable impedance control circuit of an output driver of an input/output interface is provided. The programmable impedance control circuit includes a pull-up impedance programmed according to a multi-stage emulator and a pull-down impedance programmed according to the multi-stage emulator. The multi-stage emulator includes a first stage for calibrating a pull-up PMOS impedance at a voltage level Voh, a second stage for calibrating a pull-up NMOS impedance at a voltage level Vol, a third stage for calibrating a pull-down NMOS impedance at the voltage level Vol, a fourth stage for re-calibrating the pull-up NMOS impedance at the voltage level Vol, and fifth stage for calibrating a pull-down PMOS impedance at the voltage level Voh.

Abstract: A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.

Abstract: A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, data being continuously input or output and transferred by repeatedly executing the second processsing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing,and a file storage device and a computer system utilizing

Abstract: According to the present invention, an input buffer circuit comprises a first and a second buffer circuits operated at different first and second drive voltages and connected in turn, and an output potential control circuit is provided for carrying out a control so that, in spite of a voltage value of the first drive voltage, a threshold of an output potential of the first buffer circuit becomes a threshold of an input potential of the second buffer circuit. Further, the output potential control circuit is configured such that the first buffer circuit is constituted by a pair of complementary current mirror amplifiers, and comprises feedback control means for carrying out feedback-control to the generation of the output potential for the first buffer circuit on the basis of an output potential on a reference side of this current mirror amplifier.

Abstract: A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.

Abstract: According to the present invention, an input buffer circuit comprises a first and a second buffer circuits operated at different first and second drive voltages and connected in turn, and an output potential control circuit is provided for carrying out a control so that, in spite of a voltage value of the first drive voltage, a threshold of an output potential of the first buffer circuit becomes a threshold of an input potential of the second buffer circuit. Further, the output potential control circuit is configured such that the first buffer circuit is constituted by a pair of complementary current mirror amplifiers, and comprises feedback control means for carrying out feedback-control to the generation of the output potential for the first buffer circuit on the basis of an output potential on a reference side of this current mirror amplifier.

Abstract: The present invention is proposed to attain the higher speed and lower electric power consumption in an amplifying circuit, wherein the amplifying circuit comprises a differential type amplifying circuit, a latch type amplifying circuit, and a switching circuit for switching the differential type amplifying circuit and the latch type amplifying circuit. In this configuration, the differential type amplifying circuit and the latch type amplifying circuit have a common load. Further in the present amplifying circuit, the switching circuit stops the operation of the differential type amplifying circuit after starting the operation of the latch type amplifying circuit.