Patents by Inventor Katsuya Nishiyama
Katsuya Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240265984Abstract: According to one embodiment, a memory device includes a first memory cell and a sequencer. The first memory cell is configured to store multi-bit data with a k-value threshold voltage level (k is an integer of 2 or larger). The sequencer is configured to execute a write operation having a loop process including a program operation and a verify operation. The program operation includes a first program process and a second program process. The sequencer is further configured to cause the first memory cell to store data by either the first program process or the second program process according to data to be written into the first memory cell in the write operation.Type: ApplicationFiled: February 5, 2024Publication date: August 8, 2024Applicant: Kioxia CorporationInventors: Noboru SHIBATA, Kikuko SUGIMAE, Yusuke ARAYASHIKI, Katsuya NISHIYAMA, Motohiko FUJIMATSU, Akiyuki MURAYAMA
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Patent number: 11978501Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.Type: GrantFiled: June 16, 2022Date of Patent: May 7, 2024Assignee: Kioxia CorporationInventors: Akiyuki Murayama, Kikuko Sugimae, Katsuya Nishiyama, Yusuke Arayashiki, Motohiko Fujimatsu, Kyosuke Sano, Noboru Shibata
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Publication number: 20230253029Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.Type: ApplicationFiled: June 16, 2022Publication date: August 10, 2023Applicant: Kioxia CorporationInventors: Akiyuki MURAYAMA, Kikuko SUGIMAE, Katsuya NISHIYAMA, Yusuke ARAYASHIKI, Motohiko FUJIMATSU, Kyosuke SANO, Noboru SHIBATA
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Patent number: 11423997Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.Type: GrantFiled: March 15, 2021Date of Patent: August 23, 2022Assignee: KIOXIA CORPORATIONInventors: Akiyuki Murayama, Kikuko Sugimae, Katsuya Nishiyama, Motohiko Fujimatsu, Noboru Shibata
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Publication number: 20220084609Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.Type: ApplicationFiled: March 15, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Akiyuki MURAYAMA, Kikuko SUGIMAE, Katsuya NISHIYAMA, Motohiko FUJIMATSU, Noboru SHIBATA
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Patent number: 11208230Abstract: A printing apparatus includes a casing, an optical sensor, a second light receiving portion and an adjustment part. The optical sensor includes a light emitting portion and a first light receiving portion. The optical sensor is provided at a position in the vicinity of the outlet and located within a conveying region. The conveying region is an area through which the print medium passes. The second light receiving portion is provided in the vicinity of the optical sensor and positioned outside the conveying region where external light is perceivable. The adjustment part is configured to adjust a sensitivity in the detection of the presence of the print medium by the first light receiving portion. Adjustment of the sensitivity of the first light receiving portion is performed based on an intensity of the external light received at the second light receiving portion.Type: GrantFiled: March 30, 2020Date of Patent: December 28, 2021Assignee: BROTHER KOGYO KABUSHIKI KAISHAInventor: Katsuya Nishiyama
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Publication number: 20200407098Abstract: A printing apparatus includes a casing, an optical sensor, a second light receiving portion and an adjustment part. The optical sensor includes a light emitting portion and a first light receiving portion. The optical sensor is provided at a position in the vicinity of the outlet and located within a conveying region. The conveying region is an area through which the print medium passes. The second light receiving portion is provided in the vicinity of the optical sensor and positioned outside the conveying region where external light is perceivable. The adjustment part is configured to adjust a sensitivity in the detection of the presence of the print medium by the first light receiving portion. Adjustment of the sensitivity of the first light receiving portion is performed based on an intensity of the external light received at the second light receiving portion.Type: ApplicationFiled: March 30, 2020Publication date: December 31, 2020Inventor: Katsuya Nishiyama
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Patent number: 10305025Abstract: A magnetic memory device including a first magnetic layer selectively exhibiting a first state in which the first magnetic layer has a first magnetization direction perpendicular to a main surface thereof and a second state in which the first magnetic layer has a second magnetization direction opposite to the first magnetization direction; a second magnetic layer having a fixed magnetization direction which is perpendicular to a main surface thereof and which corresponds to the first magnetization direction, and having a top surface including a recess portion or a bottom surface including a recess portion; a third magnetic layer provided between the first magnetic layer and the second magnetic layer, and having a fixed magnetization direction which is perpendicular to a main surface thereof and which corresponds to the second magnetization direction; and a nonmagnetic layer provided between the first magnetic layer and the third magnetic layer.Type: GrantFiled: December 21, 2017Date of Patent: May 28, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Jyunichi Ozeki, Hiroyuki Ohtori, Kuniaki Sugiura, Yutaka Hashimoto, Katsuya Nishiyama
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Patent number: 10236077Abstract: According to one embodiment, a screening method includes performing a first screening operation on a memory device at a first temperature to detect a defect in magnetoresistive effect elements of the memory device, replacing a first magnetoresistive effect element that is determined as defective in the first screening operation by substituting a second magnetoresistive effect element disposed in a redundancy area of the memory device for the first magnetoresistive, and performing a second screening operation on the memory device at a second temperature higher than the first temperature if the first screening operation detects a defect. Each of the first screening operation and the second screening operation includes writing data into the magnetoresistive effect element, reading data from the magnetoresistive effect element after the writing, and determining a magnetoresistive effect element is defective when the data as written does not match the data as read.Type: GrantFiled: September 4, 2017Date of Patent: March 19, 2019Assignee: Toshiba Memory CorporationInventors: Yosuke Kobayashi, Katsuya Nishiyama
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Patent number: 10230042Abstract: A magnetoresistive effect element according to one embodiment includes: a first magnetic layer; a nonmagnetic layer; a second magnetic layer; a metal layer; and a third magnetic layer. An area of a bottom of the third magnetic layer is larger than an area of a top of the third magnetic layer. An angle between the top of the third magnetic layer and a side of the third magnetic layer is larger than an angle between a top of the second magnetic layer and a side of the second magnetic layer, or an angle between the bottom of the third magnetic layer and a side of the third magnetic layer is smaller than an angle between the bottom of the second magnetic layer and a side of the second magnetic layer.Type: GrantFiled: September 9, 2016Date of Patent: March 12, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masatoshi Yoshikawa, Hisanori Aikawa, Kazuhiro Tomioka, Shuichi Tsubata, Masaru Toko, Katsuya Nishiyama, Yutaka Hashimoto, Tatsuya Kishi
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Publication number: 20180268920Abstract: According to one embodiment, a screening method includes performing a first screening operation on a memory device at a first temperature to detect a defect in magnetoresistive effect elements of the memory device, replacing a first magnetoresistive effect element that is determined as defective in the first screening operation by substituting a second magnetoresistive effect element disposed in a redundancy area of the memory device for the first magnetoresistive, and performing a second screening operation on the memory device at a second temperature higher than the first temperature if the first screening operation detects a defect. Each of the first screening operation and the second screening operation includes writing data into the magnetoresistive effect element, reading data from the magnetoresistive effect element after the writing, and determining a magnetoresistive effect element is defective when the data as written does not match the data as read.Type: ApplicationFiled: September 4, 2017Publication date: September 20, 2018Inventors: Yosuke KOBAYASHI, Katsuya NISHIYAMA
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Publication number: 20180114897Abstract: A magnetic memory device including a first magnetic layer selectively exhibiting a first state in which the first magnetic layer has a first magnetization direction perpendicular to a main surface thereof and a second state in which the first magnetic layer has a second magnetization direction opposite to the first magnetization direction; a second magnetic layer having a fixed magnetization direction which is perpendicular to a main surface thereof and which corresponds to the first magnetization direction, and having a top surface including a recess portion or a bottom surface including a recess portion; a third magnetic layer provided between the first magnetic layer and the second magnetic layer, and having a fixed magnetization direction which is perpendicular to a main surface thereof and which corresponds to the second magnetization direction; and a nonmagnetic layer provided between the first magnetic layer and the third magnetic layer.Type: ApplicationFiled: December 21, 2017Publication date: April 26, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Jyunichi OZEKI, Hiroyuki OHTORI, Kuniaki SUGIURA, Yutaka HASHIMOTO, Katsuya NISHIYAMA
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Patent number: 9882119Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer selectively exhibiting a first state in which the first magnetic layer has a first magnetization direction perpendicular to a main surface thereof and a second state in which the first magnetic layer has a second magnetization direction opposite to the first magnetization direction, a second magnetic layer having a fixed magnetization direction perpendicular to a main surface thereof and corresponding to the first magnetization direction, a third magnetic layer provided between the first and second magnetic layers, having a fixed magnetization direction perpendicular to a main surface thereof and corresponding to the second magnetization direction, and having a side surface including a recess portion, and a nonmagnetic layer provided between the first and third magnetic layers.Type: GrantFiled: September 20, 2016Date of Patent: January 30, 2018Assignee: Toshiba Memory CorporationInventors: Jyunichi Ozeki, Hiroyuki Ohtori, Kuniaki Sugiura, Yutaka Hashimoto, Katsuya Nishiyama
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Publication number: 20170263852Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer selectively exhibiting a first state in which the first magnetic layer has a first magnetization direction perpendicular to a main surface thereof and a second state in which the first magnetic layer has a second magnetization direction opposite to the first magnetization direction, a second magnetic layer having a fixed magnetization direction perpendicular to a main surface thereof and corresponding to the first magnetization direction, a third magnetic layer provided between the first and second magnetic layers, having a fixed magnetization direction perpendicular to a main surface thereof and corresponding to the second magnetization direction, and having a side surface including a recess portion, and a nonmagnetic layer provided between the first and third magnetic layers.Type: ApplicationFiled: September 20, 2016Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jyunichi OZEKI, Hiroyuki OHTORI, Kuniaki SUGIURA, Yutaka HASHIMOTO, Katsuya NISHIYAMA
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Publication number: 20170256705Abstract: A magnetoresistive effect element according to one embodiment includes: a first magnetic layer; a nonmagnetic layer; a second magnetic layer; a metal layer; and a third magnetic layer. An area of a bottom of the third magnetic layer is larger than an area of a top of the third magnetic layer. An angle between the top of the third magnetic layer and a side of the third magnetic layer is larger than an angle between a top of the second magnetic layer and a side of the second magnetic layer, or an angle between the bottom of the third magnetic layer and a side of the third magnetic layer is smaller than an angle between the bottom of the second magnetic layer and a side of the second magnetic layer.Type: ApplicationFiled: September 9, 2016Publication date: September 7, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masatoshi YOSHIKAWA, Hisanori AIKAWA, Kazuhiro TOMIOKA, Shuichi TSUBATA, Masaru TOKO, Katsuya NISHIYAMA, Yutaka HASHIMOTO, Tatsuya KISHI
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Patent number: 9653138Abstract: A memory includes a first magnetic layer, a second magnetic layer, a nonmagnetic layer between the first and second magnetic layers, a third magnetic layer synthetic-antiferromagnetic-coupled with the second magnetic layer, and a controller controlling a read operation and a write operation. The write operation includes a first operation, a second operation and a third operation. A first potential of the first magnetic layer is larger than a second potential of the third magnetic layer in the first operation. A third potential of the third magnetic layer is larger than a fourth potential of the first magnetic layer in the second operation. A fifth potential of the first magnetic layer is larger than a sixth potential of the third magnetic layer in the third operation.Type: GrantFiled: September 13, 2016Date of Patent: May 16, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yutaka Hashimoto, Katsuya Nishiyama
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Patent number: 9590174Abstract: According to one embodiment, a manufacturing method of a magnetoresistive memory device includes forming a first magnetic layer on a substrate, forming a magnetoresistive effect element on the first magnetic layer, forming a mask on a part of the magnetoresistive effect element, selectively etching the magnetoresistive effect element using the mask, forming a sidewall insulating film on a sidewall of the magnetoresistive effect element exposed by the etching, selectively etching the first magnetic layer using the mask and the sidewall insulating film and forming a deposition layer containing a magnetic material on a sidewall of the first magnetic layer and the sidewall insulating film, and introducing ions into the deposition layer.Type: GrantFiled: February 23, 2015Date of Patent: March 7, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masaru Toko, Kuniaki Sugiura, Yutaka Hashimoto, Katsuya Nishiyama, Tadashi Kai
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Patent number: 9385307Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer having a perpendicular and invariable magnetization, a first nonmagnetic insulating layer on the first magnetic layer, a second magnetic layer on the first nonmagnetic insulating layer, the second magnetic layer having a perpendicular and variable magnetization, a second nonmagnetic insulating layer on the second magnetic layer, and a nonmagnetic conductive layer on the second nonmagnetic insulating layer. The second nonmagnetic insulating layer includes a first metal oxide with a predetermined element. The first nonmagnetic insulating layer includes a second metal oxide.Type: GrantFiled: March 10, 2015Date of Patent: July 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Katsuya Nishiyama, Koji Yamakawa
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Patent number: 9373776Abstract: According to one embodiment, a magnetoresistive element includes first and second magnetic layers and a first nonmagnetic layer. The first magnetic layer has an axis of easy magnetization perpendicular to a film plane, and a variable magnetization. The second magnetic layer has an axis of easy magnetization perpendicular to a film plane, and an invariable magnetization. The first nonmagnetic layer is provided between the first and second magnetic layers. The second magnetic layer includes third and fourth magnetic layers, and a second nonmagnetic layer formed between the third and fourth magnetic layers. The third magnetic layer is in contact with the first nonmagnetic layer and includes Co and at least one of Zr, Nb, Mo, Hf, Ta, and W.Type: GrantFiled: December 12, 2014Date of Patent: June 21, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshihiko Nagase, Eiji Kitagawa, Katsuya Nishiyama, Tadashi Kai, Koji Ueda, Daisuke Watanabe
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Publication number: 20160104834Abstract: According to one embodiment, a manufacturing method of a magnetoresistive memory device includes forming a first magnetic layer on a substrate, forming a magnetoresistive effect element on the first magnetic layer, forming a mask on a part of the magnetoresistive effect element, selectively etching the magnetoresistive effect element using the mask, forming a sidewall insulating film on a sidewall of the magnetoresistive effect element exposed by the etching, selectively etching the first magnetic layer using the mask and the sidewall insulating film and forming a deposition layer containing a magnetic material on a sidewall of the first magnetic layer and the sidewall insulating film, and introducing ions into the deposition layer.Type: ApplicationFiled: February 23, 2015Publication date: April 14, 2016Inventors: Masaru TOKO, Kuniaki SUGIURA, Yutaka HASHIMOTO, Katsuya NISHIYAMA, Tadashi KAI