Patents by Inventor Katsuya Ogata

Katsuya Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094644
    Abstract: A substrate treatment apparatus includes: a plurality of solution treatment modules stacked at multiple stages, each configured to perform a treatment using a treatment solution on a substrate; and a solution supply unit configured to supply the treatment solution to the plurality of solution treatment modules, wherein: the solution supply unit includes supply pipelines provided with a solution feeder corresponding to the solution treatment modules; and the solution feeder includes a pump configured to pressure-feed the treatment solution to the corresponding solution treatment module and a filter configured to filtrate the treatment solution, and is arranged adjacent to the corresponding solution treatment module in a horizontal direction.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 21, 2024
    Inventors: Makoto OGATA, Katsuya HASHIMOTO, Katsunori ICHINO, Masataka TANAKA, Kazuya KUDO
  • Publication number: 20220251519
    Abstract: A concentration membrane for use in concentrating biological particles, including: a hydrophilic composite porous membrane including: a porous substrate; and a hydrophilic resin with which at least one main surface and inner surfaces of pores of the porous substrate are coated, the hydrophilic composite porous membrane having a ratio t/x of a membrane thickness t (m) to an average pore diameter x (m), as measured with a perm porometer, of from 50 to 630.
    Type: Application
    Filed: January 28, 2020
    Publication date: August 11, 2022
    Applicants: TEIJIN LIMITED, VISGENE, LTD.
    Inventors: Mami NAMBU, Yoshikazu IKUTA, Yu NAGAO, Kunihiro KAIHATSU, Ikuko YUMEN, Katsuya OGATA, Daisuke AOKI
  • Patent number: 9021405
    Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takanori Hiramoto, Toshio Hino, Tsuyoshi Sakata, Yutaka Mizuno, Katsuya Ogata
  • Patent number: 8386991
    Abstract: A design support apparatus includes: a circuit-data generation unit to generate circuit data based on layout information of a semiconductor integrated circuit; and a parameter determination unit to set a first parameter relating to mechanical stress exerted on a transistor including at least one of a plurality of gates in a diffusion region, wherein the circuit-data generation unit obtains a mobility of the transistor based on the first parameter and reflects the mobility in the circuit data.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 26, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Katsuya Ogata, Hiroyuki Rokugawa
  • Publication number: 20120329266
    Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 27, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takanori Hiramoto, Toshio Hino, Tsuyoshi Sakata, Yutaka Mizuno, Katsuya Ogata
  • Publication number: 20110161910
    Abstract: A design support apparatus includes: a circuit-data generation unit to generate circuit data based on layout information of a semiconductor integrated circuit; and a parameter determination unit to set a first parameter relating to mechanical stress exerted on a transistor including at least one of a plurality of gates in a diffusion region, wherein the circuit-data generation unit obtains a mobility of the transistor based on the first parameter and reflects the mobility in the circuit data.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 30, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuya OGATA, Hiroyuki Rokugawa
  • Patent number: 4802840
    Abstract: An extrusion die for forming a honeycomb stucture has a lattice molding groove formed in the outlet surface of the die body. In the inlet surface of the die body there are formed plural independent supply passages that are opposite to the intersecting portions of the molding groove and extend toward the outlet surface. A through hole is designed to communicate adjacent supply passages at a place that forms part of the partition wall between the supply passages and contacts with the molding groove. This through hole takes the combined shape of a trapezoid with the width of the molding groove as its top side and with the diameter of the supply passage as its maximum base side and a semicircle having said base side as its diameter.
    Type: Grant
    Filed: November 25, 1987
    Date of Patent: February 7, 1989
    Assignees: Catalysts & Chemicals Industries Co., Ltd., Iwao Jiki Kogyo Co., Ltd.
    Inventors: Morio Fukuda, Masayuki Hanada, Hideo Inutsuka, Katsuya Ogata