Patents by Inventor Katsuya Shino

Katsuya Shino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5279979
    Abstract: A method of manufacturing a semiconductor device includes the steps of: forming a gate electrode and a wiring layer on a silicon oxide film formed on the surface of a semiconductor substrate, by using conductive material; forming a diffusion region on the surface of the semiconductor substrate by implanting impurities into the semiconductor substrate at an area other than the gate electrode and the wiring layer; and forming a film for electrically interconnecting the diffusion region and the wiring layer, using conductive material.
    Type: Grant
    Filed: May 20, 1992
    Date of Patent: January 18, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuya Shino, Koushi Maeda
  • Patent number: 5256894
    Abstract: The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer doped with an impurity and a refractory metal silicide layer has an impurity concentration that is reduced close to a boundary between the polysilicon layer and the refractory metal silicide layer. With this structure, the difference in oxidation speed between the polysilicon layer and the silicide layer is smaller in comparison with a conventional structure, and thus peeling due to bird's beaks can be prevented. The semiconductor device of this structure can be realized by a two-layer polysilicon structure in which the upper layer in contact with the refractory metal silicide layer has a lower impurity concentration, or by a structure in which the peak of the impurity concentration profile is set to be deep within the polysilicon layer during ion implantation.
    Type: Grant
    Filed: July 12, 1991
    Date of Patent: October 26, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuya Shino
  • Patent number: 5238873
    Abstract: A method for manufacturing a semiconductor device, comprising the steps of forming an oxide film selectively on the surface of a semiconductor substrate; forming a first polycrystalline silicon film on the whole surface and then forming a metallic silicide film on the surface of the first polycrystalline silicon film; patterning the first polycrystalline silicon film and the metallic silicide film except for the desired areas by a lithographic method; depositing polycrystalline silicon on the whole surface to thereby form a second polycrystalline silicon film and allow it to cover the patterned first polycrystalline silicon film and metallic silicide film; and performing oxidation in a state in which a boundary portion between the first polycrystalline silicon film and the metallic silicide film is not exposed to an oxidizing atmosphere by the presence of the second polycrystalline silicon film, to form an oxide film on the surface.
    Type: Grant
    Filed: October 2, 1991
    Date of Patent: August 24, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayoshi Higashizono, Yasunobu Kodaira, Katsuya Shino