Patents by Inventor Katsuya Tabuchi
Katsuya Tabuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8691619Abstract: This invention aims to provide a laminated structure and an integrated structure of a high production efficiency for a CIS based thin-film solar cell, which can produce a high-resistance buffer layer of the CIS based thin-film solar cell efficiently on a series of production lines and which needs no treatment of wastes or the like, and a manufacturing method for the structures. The CIS based thin-film solar cell includes a back electrode, a p-type CIS based light absorbing layer, a high-resistance buffer layer and an n-type transparent conductive film laminated in this order. The high-resistance buffer layer and the n-type transparent conductive film are formed of thin films of a zinc oxide group. The buffer layer contacts the p-type CIS based light absorbing layer directly, and has a resistivity of 500?·cm or higher.Type: GrantFiled: November 25, 2008Date of Patent: April 8, 2014Assignee: Showa Shell Sekiyu, K.K.Inventors: Hideki Hakuma, Katsuya Tabuchi, Yosuke Fujiwara, Katsumi Kushiya
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Patent number: 8614114Abstract: A treatment object containing any one of Cu/Ga, Cu/In and Cu—Ga/In is held in a heated state at a temperature T1 for a time ?t1 in such a state that a selenium source is introduced, thereby forming a selenide. Thereafter, a sulfur source is introduced to replace the atmosphere in the system with a sulfur atmosphere. In this state, the treatment object is held in a heated state at a temperature T2 for a time ?t2. The temperature of the treatment object is then decreased to T3, and, at that temperature, the treatment object is held in a heated state for a time ?t3.Type: GrantFiled: November 28, 2008Date of Patent: December 24, 2013Assignee: Showa Shell Sekiyu K.K.Inventors: Hideki Hakuma, Yuri Yamaguchi, Katsuya Tabuchi, Katsumi Kushiya
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Publication number: 20100311202Abstract: A treatment object containing any one of Cu/Ga, Cu/In and Cu—Ga/In is held in a heated state at a temperature T1 for a time ?t1 in such a state that a selenium source is introduced, thereby forming a selenide. Thereafter, a sulfur source is introduced to replace the atmosphere in the system with a sulfur atmosphere. In this state, the treatment object is held in a heated state at a temperature T2 for a time ?t2. The temperature of the treatment object is then decreased to T3, and, at that temperature, the treatment object is held in a heated state for a time ?t3.Type: ApplicationFiled: November 28, 2008Publication date: December 9, 2010Applicant: SHOWA SHELL SEKIYU K.K.Inventors: Hideki Hakuma, Yuri Yamaguchi, Katsuya Tabuchi, Katsumi Kushiya
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Publication number: 20100267190Abstract: This invention aims to provide a laminated structure and an integrated structure of a high production efficiency for a CIS based thin-film solar cell, which can produce a high-resistance buffer layer of the CIS based thin-film solar cell efficiently on a series of production lines and which needs no treatment of wastes or the like, and a manufacturing method for the structures. The CIS based thin-film solar cell includes a back electrode, a p-type CIS based light absorbing layer, a high-resistance buffer layer and an n-type transparent conductive film laminated in this order. The high-resistance buffer layer and the n-type transparent conductive film are formed of thin films of a zinc oxide group. The buffer layer contacts the p-type CIS based light absorbing layer directly, and has a resistivity of 500 ?·cm or higher.Type: ApplicationFiled: November 25, 2008Publication date: October 21, 2010Inventors: Hideki Hakuma, Katsuya Tabuchi, Yosuke Fujiwara, Katsumi Kushiya
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Publication number: 20080303087Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: ApplicationFiled: April 24, 2008Publication date: December 11, 2008Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Patent number: 7365392Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: GrantFiled: December 14, 2004Date of Patent: April 29, 2008Assignee: Fuji Electric Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Patent number: 7256086Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.Type: GrantFiled: January 10, 2006Date of Patent: August 14, 2007Assignee: Fuji Electric Co., Ltd.Inventors: Katsuya Tabuchi, Naoto Fujishima, Mutsumi Kitamura, Akio Sugi
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Publication number: 20060110875Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.Type: ApplicationFiled: January 10, 2006Publication date: May 25, 2006Applicant: Fuji Electric Co., Ltd.Inventors: Katsuya Tabuchi, Naoto Fujishima, Mutsumi Kitamura, Akio Sugi
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Patent number: 7034377Abstract: To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.Type: GrantFiled: November 24, 2003Date of Patent: April 25, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi
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Patent number: 7012301Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.Type: GrantFiled: December 18, 2002Date of Patent: March 14, 2006Assignee: Fuji Electric Co., Ltd.Inventors: Katsuya Tabuchi, Naoto Fujishima, Mutsumi Kitamura, Akio Sugi
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Publication number: 20050087800Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: ApplicationFiled: December 14, 2004Publication date: April 28, 2005Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Patent number: 6858500Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: GrantFiled: December 31, 2002Date of Patent: February 22, 2005Assignee: Fuji Electric Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Publication number: 20040178445Abstract: To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.Type: ApplicationFiled: November 24, 2003Publication date: September 16, 2004Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi
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Publication number: 20030164527Abstract: Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.Type: ApplicationFiled: December 31, 2002Publication date: September 4, 2003Applicant: Fuji Electric Co., Ltd.Inventors: Akio Sugi, Naoto Fujishima, Mutsumi Kitamura, Katsuya Tabuchi, Setsuko Wakimoto
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Publication number: 20030132460Abstract: A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.Type: ApplicationFiled: December 18, 2002Publication date: July 17, 2003Applicant: Fuji Electric Co., Ltd.Inventors: Katsuya Tabuchi, Naoto Fujishima, Mutsumi Kitamura, Akio Sugi