Abstract: A first node and a second node transmit packets to a third node via a switch. The packets are buffered in a Tx buffer in the switch and then transmitted to the third node. When the third node detects a sign of congestion at the Tx buffer based on the reception frequency of the packets, it is recognized, from transmitter addresses included in the received packets, that the nodes transmitting the packets to the third node are the first node and the second node, and a control packet for a transmission stop request is transmitted to the first node and the second node. On receiving the control packet for a transmission stop request, the first node stops transmission of only packets addressed to the third node. On receiving the control packet for a transmission stop request, the second node stops transmission of only packets addressed to the third node.

Abstract: A first node and a second node transmit packets to a third node via a switch. The packets are buffered in a Tx buffer in the switch and then transmitted to the third node. When the third node detects a sign of congestion at the Tx buffer based on the reception frequency of the packets, it is recognized, from transmitter addresses included in the received packets, that the nodes transmitting the packets to the third node are the first node and the second node, and a control packet for a transmission stop request is transmitted to the first node and the second node. On receiving the control packet for a transmission stop request, the first node stops transmission of only packets addressed to the third node. On receiving the control packet for a transmission stop request, the second node stops transmission of only packets addressed to the third node.

Abstract: An information processing apparatus includes: a central processing device; a storage device that stores a first instruction group and a second instruction group in a storage area to which a predetermined address range in an address space is assigned; and a circuit that executes predetermined arithmetic processing according to an address assigned in the address space. The central processing device includes: a program counter that designates an address; a controller that outputs an address obtained as a result of execution of the first instruction group to the program counter; and a translator including a memory that stores an address assigned to the circuit as a second address, in association with an address used for execution of the second instruction group, the address being a first address, the translator outputting the second address to the program counter when the address output from the controller matches the first address.

Abstract: A first processor included in a transmission device stores a first generator polynomial in a portion of a first data scrambled by using the first generator polynomial, and transmits the first data including the first generator polynomial. A second processor included in a reception device receives the first data, descrambles the first data by using the first generator polynomial, and generates a second data by scrambling the descrambled first data by using a second generator polynomial different from the first generator polynomial.

Abstract: A data storage apparatus includes: a memory configured to store data; an input delay circuit configured to input a set of data of a plurality of bits into the memory at different timings between the plurality of bits by adding different delays to the plurality of bits in the set of data or by adding different delays to bits in bit groups obtained by grouping the plurality of bits in units of a consecutive bits; and an output delay circuit configured to obtain an original set of data, which is the set of data before the input delay circuit adds the different delays, by adding, to the plurality of bits in the set of data output from the memory, delays having a pattern opposite that of the delays added by the input delay circuit.

Abstract: A data storage apparatus includes: a memory configured to store data; an input delay circuit configured to input a set of data of a plurality of bits into the memory at different timings between the plurality of bits by adding different delays to the plurality of bits in the set of data or by adding different delays to bits in bit groups obtained by grouping the plurality of bits in units of a consecutive bits; and an output delay circuit configured to obtain an original set of data, which is the set of data before the input delay circuit adds the different delays, by adding, to the plurality of bits in the set of data output from the memory, delays having a pattern opposite that of the delays added by the input delay circuit.

Abstract: A clock change method includes: converting the serial data synchronized to a first clock into parallel data; latching the serial-to-parallel converted data into a designated data storing circuit with a latch timing that occurs once in every a number of clock cycles of a second clock; and converting the latched parallel data into the serial data synchronized to the second clock, and wherein: each time a packet of serial data synchronized to the first clock is received, a timing adjustment is performed to adjust the latch timing so that the latch timing occurs a predetermined time after occurrence of a conversion timing for converting the serial data synchronized to the first clock into the parallel data.

Abstract: A route selecting method includes performing a route search for obtaining route information from destination information contained in a received packet; attaching the route information obtained by the route search to the received packet; storing the packet having the route information in a buffer; reading the packet stored in the buffer sequentially from the route information attached to the packet; selecting an output route for the packet read from the buffer based on the route information read from the buffer; and outputting the packet via the selected output route.

Abstract: A clock change method includes: converting the serial data synchronized to a first clock into parallel data; latching the serial-to-parallel converted data into a designated data storing circuit with a latch timing that occurs once in every a number of clock cycles of a second clock; and converting the latched parallel data into the serial data synchronized to the second clock, and wherein: each time a packet of serial data synchronized to the first clock is received, a timing adjustment is performed to adjust the latch timing so that the latch timing occurs a predetermined time after occurrence of a conversion timing for converting the serial data synchronized to the first clock into the parallel data.

Abstract: A route selecting method includes performing a route search for obtaining route information from destination information contained in a received packet; attaching the route information obtained by the route search to the received packet; storing the packet having the route information in a buffer; reading the packet stored in the buffer sequentially from the route information attached to the packet; selecting an output route for the packet read from the buffer based on the route information read from the buffer; and outputting the packet via the selected output route.

Abstract: A packet switch apparatus for switching a packet between a plurality of input ports and a plurality of output ports includes a plurality of input buffers for storing a packet inputted to the input port, a plurality of output buffers for storing a packet outputted to the output port, and a path controller for transmitting the packet stored in the input buffer to the output buffer on the basis of path information of the packet stored in the input buffer by a higher transfer rate than an input rate for receiving the packet at the input port.

Abstract: In a cell assembling method and device for packets received from a plurality of input ports, packets received from e.g. four input ports are respectively stored in packet buffers. By sequentially and cyclically providing a read request to the packet buffers at regular intervals, the packets per fixed length data are sequentially and cyclically read. Then, by capsulating the fixed length data read (any one of fixed length data), the data is converted into e.g. an ATM cell. Alternatively, based on cell assembling information (any one of cell assembling information synchronized with fixed length data), e.g. an ATM header is generated to be used for a conversion into the ATM cell.

Abstract: In a frame communication method and device which can accurately reproduce received frames without being influenced by fluctuations of a frame interval caused by inter-channel multiplexing on a transmitting side, a frame interval is detected from transmission frames; information of the frame interval is added to the transmission frames; the transmission frames are multiplexed and transmitted. Also, the information of the frame interval is extracted from received frames demultiplexed; and the received frames are spaced by the frame interval to be transferred. When the frame interval exceeds a maximum frame interval determined by a bit number of the information of the frame interval, only information of the maximum frame interval is transmitted and information of subsequent remaining frame intervals is added to the transmission frames to be transmitted.