Abstract: According to one embodiment, a semiconductor device includes a stacked body and a pillar. The stacked body includes insulating films, electrode films, and silicon containing films. Each of the insulating films and each of the electrode films are stacked alternately. One of the silicon containing films is provided between one of the insulating films and one of the electrode films. The pillar extends in the stacked body in a stacking direction of the insulating films and the electrode films. The pillar includes a silicon pillar and a memory film. The silicon pillar extends in the stacking direction. The memory film is provided between the silicon pillar and one of the electrode films.

Abstract: According to one embodiment, a semiconductor device includes a stacked body and a pillar. The stacked body includes insulating films, electrode films, and silicon containing films. Each of the insulating films and each of the electrode films are stacked alternately. One of the silicon containing films is provided between one of the insulating films and one of the electrode films. The pillar extends in the stacked body in a stacking direction of the insulating films and the electrode films. The pillar includes a silicon pillar and a memory film. The silicon pillar extends in the stacking direction. The memory film is provided between the silicon pillar and one of the electrode films.

Abstract: According to one embodiment, a semiconductor device includes a stacked body and a pillar. The stacked body includes insulating films, electrode films, and silicon containing films. Each of the insulating films and each of the electrode films are stacked alternately. One of the silicon containing films is provided between one of the insulating films and one of the electrode films. The pillar extends in the stacked body in a stacking direction of the insulating films and the electrode films. The pillar includes a silicon pillar and a memory film. The silicon pillar extends in the stacking direction. The memory film is provided between the silicon pillar and one of the electrode films.

Abstract: A semiconductor manufacturing apparatus according to an embodiment includes a heater, a sidewall, and a moving mechanism. The heater is capable of heating a semiconductor substrate. The sidewall is located at an outer edge of the heater and protrudes upward from a mount face of the heater on which the semiconductor substrate is mounted. The moving mechanism relatively moves at least a part of the sidewall and the heater in a substantially perpendicular direction with respect to the mount face.

Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a plurality of films above a substrate in a same chamber without transferring the substrate out of the chamber, forming a target film to be polished above the plurality of films, and polishing the target film by a chemical mechanical polishing (CMP) technique using a film on a front side among the plurality of films as a polishing stopper.

Abstract: A method of fabricating a semiconductor device including depositing a first silicon oxide film on a silicon substrate, depositing a silicon-containing film on the first silicon oxide film, applying a coating solution for silica film formation over the silicon-containing film, and heat-treating the coating solution, thereby forming a second silicon oxide film.

Abstract: A method of fabricating a semiconductor device including depositing a first silicon oxide film on a silicon substrate, depositing a silicon-containing film on the first silicon oxide film, applying a coating solution for silica film formation over the silicon-containing film, and heat-treating the coating solution, thereby forming a second silicon oxide film.

Abstract: A first aspect of the present invention is providing a non-volatile semiconductor memory device, comprising: a memory cell having a tunnel oxide layer formed on a semiconductor substrate, a floating gate formed on the tunnel oxide layer, a control gate to which voltage is supplied, a source diffusion layer and a drain diffusion layer, the source and drain diffusion layers formed in the semiconductor substrate adjacent to the tunnel oxide layer; a contact layer connected to the drain diffusion layer; and a layer formed above the memory cell, the layer comprising at least one of: 1) a silicon oxide layer to which nitrogen are doped, 2) a silicon oxide layer to which aluminum are doped, 3) an aluminum oxide layer, 4) a silicon oxide layer to which titanium are doped, 5) a silicon oxide layer to which two of nitrogen, aluminum, and titanium are doped, 6) a silicon oxide layer to which nitrogen, aluminum, and titanium are doped, 7) a titanium oxide layer, 8) a titanium and aluminum oxide layer, 9) a simple metal l

Abstract: A semiconductor manufacturing apparatus includes a main piping distributing an insulating film forming chemical solution onto a semiconductor substrate, and an auxiliary piping provided so as to surround the main piping so that a liquid chemically nonreactive to the insulating film forming chemical solution flows therethrough.

Abstract: A semiconductor device manufacturing method includes forming a wiring layer, and forming a first insulating film on the wiring layer under a condition that hydrogen in a plasma is 1% or less in all gas components.

Abstract: A semiconductor device includes a silicon substrate, a first silicon oxide film deposited on the silicon substrate, a silicon-rich film deposited on the first silicon oxide film, and a second silicon film deposited on the silicon-rich film and formed by heat-treating a fluid applied for forming a silica coat.

Abstract: A semiconductor device manufacturing method includes forming a wiring layer, and forming a first insulating film on the wiring layer under a condition that hydrogen in a plasma is 1% or less in all gas components.

Abstract: A first aspect of the present invention is providing a semiconductor memory device having a gate electrode, comprising a memory cell having the gate, a source electrode, and a drain electrode; and a layer formed above the memory cell, the layer comprising at least one of: 1) a silicon oxide layer to which nitrogen are doped, 2) a silicon oxide layer to which aluminum are doped, 3) an aluminum oxide layer, 4) a silicon oxide layer to which titanium are doped, 5) a silicon oxide layer to which two of nitrogen, aluminum, and titanium are doped, 6) a silicon oxide layer to which nitrogen, aluminum, and titanium are doped, 7) a titanium oxide layer, 8) a titanium and aluminum oxide layer, 9) a simple metal layer comprising one of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, 10) an alloy layer comprising at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, and the at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc being included 50% or more, 11) a nitrogenous layer of the alloy layer

Abstract: There is disclosed a polishing technology without generation of corrosion on an Al-Cu film formed damascene wiring on a semiconductor substrate by the CMP technology. A chelating agent which forms a chelate compound together with Al and Cu, or a chemical substance which is absorbed onto Al and Cu is added into a slurry to polish, and then a thin film of the chelate compound or the chemical substance is formed on the Al-Cu film. This thin film can suppress movement of electrons (cell reaction) from Al to Cu caused in polishing and suppress elution of Al from the Al-Cu film.