Abstract: The disclosed is a method for synchronization of the running key that is generated from a shared key and that is used for encryption and decryption in communications encrypted with the shared key using a multi-valued signal. In the method for synchronization, the transmitting node transmits a signal that is formed of a multi-valued signal and that has a predetermined fixed pattern before transmitting data encrypted with the shared key. The receiving node generates a bit discrimination threshold signal that allows for bit discrimination and that has a fixed length, shifts bit by bit the phase of the bit discrimination threshold signal while monitoring bit discrimination with respect to a fixed pattern signal that is to be received, and sets the phase of the bit discrimination threshold signal when the phase of the fixed pattern signal matches the phase of the bit discrimination threshold signal.

Abstract: A transmitting node produces synchronization data to be inserted into plain text and encrypts the thus generated data into multi-valued data so as to transmit the data. The synchronization data indicates the position of a running key used for encryption. A receiving node decrypts a signal including the synchronization data using the running key and detects the synchronization data from the signal to confirm synchronization of the running key between transmitting and receiving nodes. Then, the receiving node transmits a synchronization confirmation signal to the transmitting node. If the transmitting node does not receive the synchronization confirmation signal, it determines that synchronization of the running key is shifted, and re-synchronization is performed. To perform re-synchronization, a running key ahead of the position of the running key associated with synchronization data that has been stored is generated.

Abstract: A transmitting node produces synchronization data to be inserted into plain text and encrypts the thus generated data into multi-valued data so as to transmit the data. The synchronization data indicates the position of a running key used for encryption. A receiving node decrypts a signal including the synchronization data using the running key and detects the synchronization data from the signal to confirm synchronization of the running key between transmitting and receiving nodes. Then, the receiving node transmits a synchronization confirmation signal to the transmitting node. If the transmitting node does not receive the synchronization confirmation signal, it determines that the synchronization of the running key is shifted, and re-synchronization is performed. To perform re-synchronization, a running key ahead of the position of the running key associated with synchronization data that has been stored is generated.

Abstract: The disclosed is a method for synchronization of the running key that is generated from a shared key and that is used for encryption and decryption in communications encrypted with the shared key using a multi-valued signal. In the method for synchronization, the transmitting node transmits a signal that is formed of a multi-valued signal and that has a predetermined fixed pattern before transmitting data encrypted with the shared key. The receiving node generates a bit discrimination threshold signal that allows for bit discrimination and that has a fixed length, shifts bit by bit the phase of the bit discrimination threshold signal while monitoring bit discrimination with respect to a fixed pattern signal that is to be received, and sets the phase of the bit discrimination threshold signal when the phase of the fixed pattern signal matches the phase of the bit discrimination threshold signal.

Abstract: The invention intends to realize a high accuracy of some picoseconds in skew compensation as well as a downsized circuit scale. A phase shifter using analog circuits that allows a downsized circuit scale and a high-accuracy phase shifting is adopted in order to finely shift the phase between a clock signal and a data signal. The phase shifter passes the clock signal or the data signal through a low pass filter having a pass band not higher than the based frequency of the clock signal to extract the frequency factors not higher than the based frequency factors. After dividing the extracted signal into plural signals, the phase shifter inputs the clock signal or the data signal having the phase shifted to plural variable gain amplifiers. Next, the phase shifter inputs the outputs from the variable gain amplifiers to an adder or a subtracter, and inputs the signal after being added or subtracted to a limit amplifier to reshape it into a rectangular wave.

Abstract: The invention intends to realize a high accuracy of some picoseconds in skew compensation as well as a downsized circuit scale. A phase shifter using analog circuits that allows a downsized circuit scale and a high-accuracy phase shifting is adopted in order to finely shift the phase between a clock signal and a data signal. The phase shifter passes the clock signal or the data signal through a low pass filter having a pass band not higher than the based frequency of the clock signal to extract the frequency factors not higher than the based frequency factors. After dividing the extracted signal into plural signals, the phase shifter inputs the clock signal or the data signal having the phase shifted to plural variable gain amplifiers. Next, the phase shifter inputs the outputs from the variable gain amplifiers to an adder or a subtracter, and inputs the signal after being added or subtracted to a limit amplifier to reshape it into a rectangular wave.

Abstract: A high-speed light emitting diode driver circuit for optical communication systems, in which an impedance circuit is provided between the collector and emitter of a drive transistor, and another impedance circuit is provided on the emitter side. The light emitting diode is connected to the collector side of the drive transistor. The light emitting diode is driven by an input pulse signal applied to the base of the drive transistor.