Patents by Inventor Katsuyoshi Kodera

Katsuyoshi Kodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105420
    Abstract: A data generation apparatus of one embodiment includes a processing unit, an evaluation unit, and a conversion unit. The processing unit designs, through optical proximity correction based on a target pattern formed on a substrate using the photomask, a mask pattern corresponding to the target pattern and including a plurality of rectangular regions. The evaluation unit evaluates the mask pattern using a cost function having, as a parameter, a jog length indicating a length of each of the rectangular regions included in the mask pattern in a first direction. The conversion unit converts mask pattern data indicating the mask pattern with an evaluation that meets a predetermined condition to drawing data corresponding to a variable shaped beam drawing process.
    Type: Application
    Filed: June 9, 2023
    Publication date: March 28, 2024
    Applicant: Kioxia Corporation
    Inventors: Katsuyoshi KODERA, Shoji MIMOTOGI, Shunko MAGOSHI, Ryuji OGAWA, Taiki KIMURA
  • Publication number: 20240096644
    Abstract: According to one embodiment, a pattern forming method uses a template having a first region with a first recessed portion and a second region adjacent to the first region. The second region has a second recessed portion therein. The recessed portions satisfy a specific relationship (D1>2(H1+H2)/?), where D1 is a shortest distance between the first and second recessed portions, H1 is a depth of the first recessed portion, and H2 is a depth of the second recessed portion. The pattern forming method includes placing an imprint material on an object and pressing the template against the material to mold the imprint material. The molded imprint material is then cured, and the template removed.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 21, 2024
    Inventors: Koki UEHA, Katsuyoshi KODERA
  • Publication number: 20230092256
    Abstract: According to one embodiment, a mark is a mark arranged on a substrate and including a line-and-space pattern having a substantially constant pitch on the substrate, the mark including: a first mark in which the line-and-space pattern extends in a direction at an angle that is less than 90° or greater than 90° with respect to the first direction, the first mark including a pair of first patterns arranged at a distance in a first direction along the substrate or a first periodic pattern having a period in the first direction; and a second mark in which the line-and-space pattern extends in a direction at an angle that is less than 90° or greater than 90° with respect to the second direction, the second mark including a pair of second patterns provided in correspondence with the pair of first patterns and arranged at a distance in a second direction along the substrate and intersecting the first direction or a second periodic pattern provided in correspondence with the first periodic pattern and having a period
    Type: Application
    Filed: March 14, 2022
    Publication date: March 23, 2023
    Applicant: Kioxia Corporation
    Inventors: Sachiko Kobayashi, Kazuya Fukuhara, Katsuyoshi KODERA, Jun Watanabe, Koki Ueha
  • Publication number: 20160071740
    Abstract: A pattern forming method according to the present embodiment forms a self-assembly material layer including a liquid-crystal material in at least one block thereof on a surface of a base material. An external field in a first region of the self-assembly material layer is applied locally, the first region of the self-assembly material layer is rubbed locally, or a film thickness of the first region of the self-assembly material layer is changed locally. The self-assembly material layer is phase-separated.
    Type: Application
    Filed: March 4, 2015
    Publication date: March 10, 2016
    Inventors: Katsuyoshi KODERA, Yoshihiro Naka
  • Publication number: 20150261904
    Abstract: According to one embodiment, a pattern data generation method includes: decomposing data of a pattern to be formed into first guide pattern data and first DSA pattern data; generating a plurality of combinations of second guide pattern data and second DSA pattern data based on combinations of the first guide pattern data and the first DSA pattern data; carrying out simulation for each of the plurality of combinations of the second guide pattern data and the second DSA pattern data, and evaluating the simulation results using a predetermined evaluation function; and extracting one set or a plurality of sets of combinations that are suitable for forming the pattern to be formed, from among the plurality of combinations of the second guide pattern data and the second DSA pattern data, based on the evaluation results.
    Type: Application
    Filed: August 21, 2014
    Publication date: September 17, 2015
    Inventors: Sachiko KOBAYASHI, Yoshihiro Naka, Masafumi Asano, Shoji Mimotogi, Katsuyoshi Kodera
  • Publication number: 20130017495
    Abstract: According to one embodiment, an interference exposure apparatus of the embodiment includes a light path changing section in which a changing element adapted to change a light path direction and a light path length of a plurality of light beams with respect to the plurality of light beams having coherency with respect to each other is arranged substantially axisymmetrically; and an adjusting section for adjusting one part of the light beam entering a substrate by intensity changing or phase changing one part of the light beam corresponding to a pattern shape to form on the substrate. A light beam exit from the light path changing section and the adjusting section is interfered on the substrate to carry out an interference exposure on the substrate.
    Type: Application
    Filed: March 12, 2012
    Publication date: January 17, 2013
    Inventors: Katsuyoshi Kodera, Satoshi Tanaka
  • Patent number: 8336006
    Abstract: According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyoshi Kodera, Chikaaki Kodama
  • Patent number: 8336000
    Abstract: According to one embodiment, a method is disclosed for determining position of an auxiliary pattern on a photomask. The method can include generating a first set for each of three or more imaging positions of an exposure optical system. The method can include generating a second set for each of the three or more imaging positions by inverse Fourier transforming each of the first set. The method can include calculating a second order differential with respect to the imaging position of an index indicating amplitude of light belonging to the second set. In addition, the method can include extracting a position where the second order differential assumes an extremal value on an imaging plane of the exposure optical system. At least part of positions on the photomask each corresponding to the position assuming the extremal value on the imaging plane is used as a formation position of the auxiliary pattern.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunobu Kai, Katsuyoshi Kodera
  • Publication number: 20120244717
    Abstract: According to one embodiment, a resin removal method is provided. In the resin removal method, near-field light is generated in a local area of a pattern concave-convex portion on a pattern master used for imprinting by irradiating the pattern master with ultraviolet light in an ashing gas atmosphere which removes resin attached to the pattern master. Then, the resin is removed from the pattern master by using the ashing gas and the near-field light.
    Type: Application
    Filed: September 15, 2011
    Publication date: September 27, 2012
    Inventors: Yingkang ZHANG, Katsuyoshi KODERA, Tetsuaki MATSUNAWA, Masanori TAKAHASHI
  • Publication number: 20120064732
    Abstract: According to one embodiment, a method is disclosed for determining position of an auxiliary pattern on a photomask. The method can include generating a first set for each of three or more imaging positions of an exposure optical system. The method can include generating a second set for each of the three or more imaging positions by inverse Fourier transforming each of the first set. The method can include calculating a second order differential with respect to the imaging position of an index indicating amplitude of light belonging to the second set. In addition, the method can include extracting a position where the second order differential assumes an extremal value on an imaging plane of the exposure optical system. At least part of positions on the photomask each corresponding to the position assuming the extremal value on the imaging plane is used as a formation position of the auxiliary pattern.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 15, 2012
    Inventors: Yasunobu Kai, Katsuyoshi Kodera
  • Publication number: 20110209107
    Abstract: According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 25, 2011
    Inventors: Katsuyoshi KODERA, Chikaaki Kodama
  • Publication number: 20110065028
    Abstract: According to the embodiments, each of a main pattern of a mask to be transferred onto a substrate by using a lithography process, a first assist pattern that improves a resolution of an on-substrate pattern obtained by transferring the main pattern onto the substrate, and a second assist pattern that suppresses a transfer property of the first assist pattern onto the substrate is placed as a mask pattern.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 17, 2011
    Inventors: Katsuyoshi KODERA, Satoshi TANAKA, Toshiya KOTANI, Soichi INOUE
  • Publication number: 20110029937
    Abstract: A pattern evaluating method includes generating a proximity pattern that affects a resolution performance of a circuit pattern around a lithography target pattern of the circuit pattern to be formed on the substrate, generating distribution information on a distribution of an influence degree to the resolution performance of the circuit pattern by using the lithography target pattern, calculating the influence degree to the resolution performance of the circuit pattern by the proximity pattern as a score by comparing the distribution information with the proximity pattern, and evaluating whether the proximity pattern is placed at an appropriate position in accordance with the circuit pattern based on the score.
    Type: Application
    Filed: July 14, 2010
    Publication date: February 3, 2011
    Inventors: Katsuyoshi KODERA, Satoshi TANAKA, Toshiya KOTANI, Shigeki NOJIMA, Soichi INOUE
  • Publication number: 20100304279
    Abstract: A phase shift mask having a plurality of mask patterns or mask data thereof is prepared, and an overlapped focus range in each of the mask patterns in a case where a result of exposure to each of the mask patterns, obtained by an exposure experiment or a lithography simulation, meets a desired dimension is obtained. A digging depth is determined at discretion based on the obtained overlapped focus range.
    Type: Application
    Filed: February 19, 2010
    Publication date: December 2, 2010
    Inventors: Akiko MIMOTOGI, Satoshi Tanaka, Masanori Takahashi, Yoko Takekawa, Takamasa Takaki, Katsuyoshi Kodera, Hideichi Kawaguchi
  • Publication number: 20100261121
    Abstract: To provide a pattern forming method comprising: laminating a resist layer on a substrate; forming a diffraction pattern having an opening opened at a predetermined pitch p for diffracting exposure light on an upper layer side of the resist layer; performing whole image exposure with respect to the diffraction pattern in which a refractive index with respect to the exposure light is n, with diffracted light acquired by irradiation of exposure light having a wavelength ? from above the diffraction pattern, which is then diffracted by the diffraction pattern; and forming a desired pattern on a lower layer side of the resist pattern by using a resist pattern formed by developing the resist layer, wherein the predetermined pitch p, the wavelength ?, and the refractive index n satisfy a condition of p>?/n.
    Type: Application
    Filed: March 4, 2010
    Publication date: October 14, 2010
    Inventors: Masanori TAKAHASHI, Satoshi Tanaka, Soichi Inoue, Akiko Mimotogi, Katsuyoshi Kodera, Takamasa Takaki
  • Publication number: 20100067777
    Abstract: An evaluation pattern generating method including dividing a peripheral area of an evaluation target pattern into a plurality of meshes; calculating an image intensity of a circuit pattern when the evaluation target pattern is transferred onto a wafer by a lithography process in a case where a mask function value is given to a predetermined mesh; calculating a mask function value of the mesh so that a cost function of the image intensity, in which an optical image characteristic amount that affects a transfer performance of the evaluation target pattern to the wafer is set to the image intensity, satisfies a predetermined reference when evaluating a lithography performance of the evaluation target pattern; and generating an evaluation pattern corresponding to the mask function value.
    Type: Application
    Filed: August 6, 2009
    Publication date: March 18, 2010
    Inventors: Katsuyoshi Kodera, Satoshi Tanaka, Shimon Maeda, Suigen Kyoh, Soichi Inoue, Ryuji Ogawa