Patents by Inventor Katsuyoshi KOGURE

Katsuyoshi KOGURE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10361086
    Abstract: In a split-gate-type MONOS memory, increase in a defective rate due to variation in a gate length of a memory gate electrode is prevented, and reliability of a semiconductor device is improved. A first dry etching having a high anisotropic property but a low selection ratio relative to silicon oxide is performed to a silicon film, and then, a second dry etching having a low anisotropic property but a high selection ratio relative to silicon oxide is performed thereto, so that a control gate electrode composed of the silicon film is formed, and then, a sidewall-shaped memory gate electrode is formed on a side surface of the control gate electrode.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Kumagae, Kazuyuki Ozeki, Katsuyoshi Kogure
  • Publication number: 20180182631
    Abstract: In a split-gate-type MONOS memory, increase in a defective rate due to variation in a gate length of a memory gate electrode is prevented, and reliability of a semiconductor device is improved. A first dry etching having a high anisotropic property but a low selection ratio relative to silicon oxide is performed to a silicon film, and then, a second dry etching having a low anisotropic property but a high selection ratio relative to silicon oxide is performed thereto, so that a control gate electrode composed of the silicon film is formed, and then, a sidewall-shaped memory gate electrode is formed on a side surface of the control gate electrode.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 28, 2018
    Inventors: Seiji KUMAGAE, Kazuyuki OZEKI, Katsuyoshi KOGURE
  • Publication number: 20170062250
    Abstract: An asking apparatus includes a load-lock chamber and an apparatus control unit. The load-lock chamber takes in or out a semiconductor wafer to or from a process chamber in which a vacuum process of the semiconductor wafer is performed. The apparatus control unit controls a venting process for putting the load-lock chamber in a vacuum state to an atmospheric state in which the load-lock chamber is opened to atmosphere. Also, the apparatus control unit compares ?1 kPa that is a pressure value previously set and a differential pressure value obtained by subtracting a second pressure value that is a pressure inside the load-lock chamber right after venting to the atmosphere from a first pressure value that is a pressure inside the load-lock chamber right before venting. The apparatus control unit outputs an alarm when the differential pressure value is lower than ?1 kPa that is a pressure value previously set.
    Type: Application
    Filed: July 27, 2016
    Publication date: March 2, 2017
    Inventors: Katsuyoshi KOGURE, Kotaro HORIKOSHI, Kaichiro KOBAYASHI, Kazuyuki OZEKI