Abstract: An input/output circuit including: a first transistor that, based on an input signal and an enable signal input to an enable terminal that switches a validity and invalidity of an output, drives a load connected between an output terminal and an external power supply; a first switch provided between the input terminal and a control terminal of the first transistor, and including a first switching terminal that switches between connecting or blocking the input signal; and a switch control section that controls the first switching terminal based on the enable signal, wherein, when a logic of the enable signal has transitioned, the switch control section controls the first switching terminal to cause the first switch to be in a connecting state for a predetermined period, to input the input signal to the control terminal of the first transistor, and to suppress a current flowing to the load.

Abstract: A semiconductor device according to the present invention has a PLL circuit which includes: a phase comparison part that detects the phase difference between a reference signal and an oscillation signal to produce a phase difference signal indicative of the phase difference in binary and then output the produces signal to outside through a first external terminal; a voltage conversion part that applies, to a phase difference voltage node, a phase difference voltage having a voltage value corresponding to the phase difference represented by the phase difference signal; an oscillation part that produces, as an oscillation signal, a signal having a frequency depending on the phase difference voltage; and a correction circuit that supplies a correction current to the phase difference voltage node, and upon reception of a test control signal at a second external terminal, supplies a current depending on the test control signal to the phase difference voltage node as a correction current.

Abstract: A semiconductor device according to the present invention has a PLL circuit which includes: a phase comparison part that detects the phase difference between a reference signal and an oscillation signal to produce a phase difference signal indicative of the phase difference in binary and then output the produces signal to outside through a first external terminal; a voltage conversion part that applies, to a phase difference voltage node, a phase difference voltage having a voltage value corresponding to the phase difference represented by the phase difference signal; an oscillation part that produces, as an oscillation signal, a signal having a frequency depending on the phase difference voltage; and a correction circuit that supplies a correction current to the phase difference voltage node, and upon reception of a test control signal at a second external terminal, supplies a current depending on the test control signal to the phase difference voltage node as a correction current.

Abstract: An input/output circuit including: a first transistor that, based on an input signal and an enable signal input to an enable terminal that switches a validity and invalidity of an output, drives a load connected between an output terminal and an external power supply; a first switch provided between the input terminal and a control terminal of the first transistor, and including a first switching terminal that switches between connecting or blocking the input signal; and a switch control section that controls the first switching terminal based on the enable signal, wherein, when a logic of the enable signal has transitioned, the switch control section controls the first switching terminal to cause the first switch to be in a connecting state for a predetermined period, to input the input signal to the control terminal of the first transistor, and to suppress a current flowing to the load.

Abstract: An oscillation circuit includes an electrical current generating portion configured to generate an electrical current having an oscillation frequency decreasing as an amplitude thereof is decreased; a control voltage generating portion configured to generate a control voltage having a magnitude decreasing as a magnitude of a power source voltage is decreased; and an electrical current control portion. The electrical current control portion includes a first input terminal connected to the control voltage generating portion for receiving the electrical current; a control terminal connected to the control voltage generating portion for receiving the control voltage; and a first output terminal. The electrical current control portion is configured to reduce the amplitude of the electrical current flowing between the first input terminal and the first output terminal as the magnitude of the control voltage is decreased.

Abstract: An oscillation circuit includes an electrical current generating portion configured to generate an electrical current having an oscillation frequency decreasing as an amplitude thereof is decreased; a control voltage generating portion configured to generate a control voltage having a magnitude decreasing as a magnitude of a power source voltage is decreased; and an electrical current control portion. The electrical current control portion includes a first input terminal connected to the control voltage generating portion for receiving the electrical current; a control terminal connected to the control voltage generating portion for receiving the control voltage; and a first output terminal. The electrical current control portion is configured to reduce the amplitude of the electrical current flowing between the first input terminal and the first output terminal as the magnitude of the control voltage is decreased.

Abstract: A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a dif

Abstract: A digital-to-analog converter includes MOS transistors formed in the identical configuration and arranged in a matrix array. Ones of the MOS transistors placed on the inner part of the array serve as constant current cells, while others placed around the inner MOS transistors function as dummy transistors and a MOS capacitance. Each dummy transistor has its gate, source and drain electrodes connected to a metal strip to which the gate electrode of each constant current cells is connected. Thus, the gate electrodes of the constant current cells are connected to a substrate or potential well via diodes consisting of the dummy transistors, thereby electric charges generated in metal strips due to plasma etching and like treatment being discharged through the diodes to the substrate or potential well. The digital-to-analog converter is thus able to produce even constant currents.

Abstract: A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a dif

Abstract: A digital-to-analog converter includes MOS transistors formed in the identical configuration and arranged in a matrix array. Ones of the MOS transistors placed on the inner part of the array serve as constant current cells, while others placed around the inner MOS transistors function as dummy transistors and a MOS capacitance. Each dummy transistor has its gate, source and drain electrodes connected to a metal strip to which the gate electrode of each constant current cells is connected. Thus, the gate electrodes of the constant current cells are connected to a substrate or potential well via diodes consisting of the dummy transistors, thereby electric charges generated in metal strips due to plasma etching and like treatment being discharged through the diodes to the substrate or potential well. The digital-to-analog converter is thus able to produce even constant currents.