Abstract: To provide a display apparatus that makes it possible to further improve a performance in controlling video presentation according to characteristics of an eyeball of a user. A display apparatus is provided that includes a light source; a processor that performs processing on a distribution of characteristics of an eyeball; a monitoring section that monitors a state of the eyeball; a matching section that performs matching on the distribution of the characteristics of the eyeball and the state of the eyeball; and an irradiator that irradiates a specified position on a retina with video display light emitted by the light source.

Abstract: A matrix converter control device includes a plurality of delay circuits which correspond to logic change timings of a plurality of input pulse width modulation (PWM) signals for controlling ON and OFF states of a plurality of switching elements included in a matrix converter. Specifically, the plurality of delay circuits are a first delay circuit, a second delay circuit, a third delay circuit, a fourth delay circuit, and a fifth delay circuit. Each of the plurality of delay circuits delays an input PWM signal by an amount of delay set for the delay circuit at a logic change timing corresponding to the delay circuit.

Abstract: A matrix converter control device includes a plurality of delay circuits which correspond to logic change timings of a plurality of input pulse width modulation (PWM) signals for controlling ON and OFF states of a plurality of switching elements included in a matrix converter. Specifically, the plurality of delay circuits are a first delay circuit, a second delay circuit, a third delay circuit, a fourth delay circuit, and a fifth delay circuit, Each of the plurality of delay circuits delays an input PWM signal by an amount of delay set for the delay circuit at a logic change timing corresponding to the delay circuit.

Abstract: A pulse-frequency control circuit includes: a selection circuit that receives, and selects from among, a plurality of reference clocks whose phases differ from one another and which have a same reference period; a setting register that stores information for identifying a setting period that is in increments of a first duration shorter than the reference period; and a control circuit that causes, based on the information stored in the setting register, the selection circuit to sequentially and repeatedly select, as a determined rising edge, a rising edge occurring at intervals of the setting period from among rising edges of the plurality of reference clocks, in which the selection circuit sequentially and repeatedly generates an output pulse whose rising edge coincides with the determined rising edge selected, to provide an output pulse sequence of the output pulses.

Abstract: A pulse-frequency control circuit includes: a selection circuit that receives, and selects from among, a plurality of reference clocks whose phases differ from one another and which have a same reference period; a setting register that stores information for identifying a setting period that is in increments of a first duration shorter than the reference period; and a control circuit that causes, based on the information stored in the setting register, the selection circuit to sequentially and repeatedly select, as a determined rising edge, a rising edge occurring at intervals of the setting period from among rising edges of the plurality of reference clocks, in which the selection circuit sequentially and repeatedly generates an output pulse whose rising edge coincides with the determined rising edge selected, to provide an output pulse sequence of the output pulses.

Abstract: In a contention avoidance control device and a contention avoidance control method for PWM output and A/D conversion, the change timings of PWM outputs are detected, and output of a received A/D conversion trigger to an A/D conversion circuit is inhibited within a predetermined time measured based on the change timings.

Abstract: In a contention avoidance control device and a contention avoidance control method for PWM output and A/D conversion, the change timings of PWM outputs are detected, and output of a received A/D conversion trigger to an A/D conversion circuit is inhibited within a predetermined time measured based on the change timings.

Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.

Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.