Patents by Inventor Katsuyuki Itoh
Katsuyuki Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8230381Abstract: With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the conventional method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. To avoid these problems, cells of a specific type specified from outside, or cells satisfying specific conditions, are extracted and arranged first or limited to a layout position by specifying a layout position, then arranging the remaining cells using a general layout algorithm.Type: GrantFiled: May 4, 2010Date of Patent: July 24, 2012Assignee: Hitachi, Ltd.Inventors: Katsuyuki Itoh, Hironori Iwamoto
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Publication number: 20100218154Abstract: With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the conventional method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. To avoid these problems, cells of a specific type specified from outside, or cells satisfying specific conditions, are extracted and arranged first or limited to a layout position by specifying a layout position, then arranging the remaining cells using a general layout algorithm.Type: ApplicationFiled: May 4, 2010Publication date: August 26, 2010Inventors: Katsuyuki Itoh, Hironori Iwamoto
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Method for designing cell layout of a semiconductor integrated circuit with logic having a data flow
Patent number: 7735040Abstract: With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. The present invention extracts cells of a specific type specified from outside or cells satisfying specific conditions, arranges these specific cells first or limits a layout position by specifying a layout position, then arranges the remaining cells using a general layout algorithm.Type: GrantFiled: January 19, 2007Date of Patent: June 8, 2010Assignee: Hitachi, Ltd.Inventors: Katsuyuki Itoh, Hironori Iwamoto -
Publication number: 20070186201Abstract: With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. The present invention extracts cells of a specific type specified from outside or cells satisfying specific conditions, arranges these specific cells first or limits a layout position by specifying a layout position, then arranges the remaining cells using a general layout algorithm.Type: ApplicationFiled: January 19, 2007Publication date: August 9, 2007Inventors: Katsuyuki ITOH, Hironori Iwamoto
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Patent number: 7251802Abstract: A wiring route deciding system, for a wiring board containing a multi-pin part, includes an input unit for receiving wiring board and wire connection information, wiring constraint information and wiring setting information, for example. The system further contains a draw wiring processing unit which decides a wiring route of a draw wiring from a part pin to a part periphery boundary based on wiring information inputted by the input unit, an inter-draw wire wiring processing unit which decides the wiring route taken between end points of the draw wiring decided by the draw wiring processing unit, and an output unit which outputs a wiring route information based on that decided by both the draw wiring processing unit and the inter-draw wire wiring processing unit. There is also provided a method counterpart for a wire routing scheme for a wiring board containing a multi-pin part.Type: GrantFiled: March 21, 2005Date of Patent: July 31, 2007Assignee: Hitachi, Ltd.Inventors: Ippei Hachiya, Tetsuo Sasaki, Katsuyuki Itoh, Hiroyuki Suzuki
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Publication number: 20050235243Abstract: By deciding a draw wiring route from a part to eliminate an intersection of wire connections generated by the part direction and the terminal arrangement order, it is possible to reduce the wiring layer used and increase the mounting density. Draw wiring processing from terminals of parts is performed prior to the entire wiring processing. In order to optimally perform the draw wiring processing, the parts connected to an object to be wired are moved onto a virtual wiring board and wiring processing is performed there. When moving a part from the real wiring board, an area around the part is cut out from the real wiring board and moved onto the virtual wiring board. On the virtual wiring board, the part direction is rotated and parallel-displaced to arrange it in the optimal state for the wiring to decide the draw wiring direction and perform wiring between the respective terminals.Type: ApplicationFiled: March 21, 2005Publication date: October 20, 2005Inventors: Ippei Hachiya, Tetsuo Sasaki, Katsuyuki Itoh, Hiroyuki Suzuki
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Patent number: 6640332Abstract: A method for determining a wiring pattern of a signal line for connection of a circuit on a multi-layer printed wiring board includes the steps of providing a constraint of an electrical length which the signal line must satisfy, determining an electrical length change at a discontinuous delay part of the signal line along which a signal propagates, determining a wiring route of the signal line, calculating an electrical length of the signal line with use of a wiring length of the signal line and the determined electrical length change, judging whether or not the calculated electrical length satisfies the electrical length constraint given to the signal line, and determining the wiring route as a wiring pattern when the electrical length constraint is satisfied as the decision result, thereby carrying out a wiring layout to make an electrical length constraint satisfied.Type: GrantFiled: May 23, 2001Date of Patent: October 28, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Mitome, Katsuyuki Itoh
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Patent number: 6627357Abstract: A reticle includes a first substrate including a first light-permeable substrate, and a first pattern formed on the first light-permeable substrate and having a first light transmittance, and a second substrate including a second light-permeable substrate, and a second pattern formed on the second light-permeable substrate and having a second light transmittance. The first and second substrates are coupled to each other such that the first and second patterns face each other. A part of the first and second patterns at which the first and second patterns overlap each other defines a light-impermeable pattern.Type: GrantFiled: April 17, 2001Date of Patent: September 30, 2003Assignee: NEC Electronics CorporationInventor: Katsuyuki Itoh
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Publication number: 20020089830Abstract: A method for determining a wiring pattern of a signal line for connection of a circuit on a multi-layer printed wiring board includes the steps of providing a constraint of an electrical length which the signal line must satisfy, determining an electrical length change at a discontinuous delay part of the signal line along which a signal propagates, determining a wiring route of the signal line, calculating an electrical length of the signal line with use of a wiring length of the signal line and the determined electrical length change, judging whether or not the calculated electrical length satisfies the electrical length constraint given to the signal line, and determining the wiring route as a wiring pattern when the electrical length constraint is satisfied as the decision result, thereby carrying out a wiring layout to make an electrical length constraint satisfied.Type: ApplicationFiled: May 25, 2001Publication date: July 11, 2002Inventors: Hiroyuki Mitome, Katsuyuki Itoh
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Publication number: 20010033977Abstract: A reticle includes a first substrate including a first light-permeable substrate, and a first pattern formed on the first light-permeable substrate and having a first light transmittance, and a second substrate including a second light-permeable substrate, and a second pattern formed on the second light-permeable substrate and having a second light transmittance. The first and second substrates are coupled to each other such that the first and second patterns face each other. A part of the first and second patterns at which the first and second patterns overlap each other defines a light-impermeable pattern.Type: ApplicationFiled: April 17, 2001Publication date: October 25, 2001Inventor: Katsuyuki Itoh
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Patent number: 6296925Abstract: An aperture plate for a charged beam drawing machine includes a body substrate having such a construction that opposite sides of a center plane in a thickness direction have the same structure. With this arrangement, it is possible to minimize a warp occurring in the course of forming the aperture plate, and therefore, the forming yield can be elevated.Type: GrantFiled: September 4, 1997Date of Patent: October 2, 2001Assignee: NEC CorporationInventor: Katsuyuki Itoh
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Patent number: 6288407Abstract: An electron beam-writing apparatus comprising a first beam-shaping aperture means and a second beam-shaping aperture means, wherein the first and/or second beam-shaping aperture means has an aperture(s) of a shape(s) corresponding to the desired patterns to be written on a semiconductor substrate; and an electron beam-writing method of improved throughput using the apparatus.Type: GrantFiled: August 25, 1997Date of Patent: September 11, 2001Assignee: NEC CorporationInventor: Katsuyuki Itoh
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Patent number: 5994036Abstract: A method of forming a resist pattern comprises the following steps. A resist is applied on a wafer for subsequent baking the same. Subsequently, the resist-applied wafer is then stored in an atmosphere maintained at a humidity of not less than 80% until the resist-applied wafer is placed in an exposure system for exposure thereof by use of a photo-mask. A development of the exposed resist on the wafer is carried out to form a resist pattern. It is possible to further store the wafer in a clean room before the exposure. The above resist is preferably a chemical sensitizing resist.Type: GrantFiled: February 24, 1997Date of Patent: November 30, 1999Assignee: NEC CorporationInventor: Katsuyuki Itoh
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Patent number: 5784150Abstract: An electron-beam cell projection lithography apparatus includes an electron-beam source, a first aperture through which an electron-beam transmitted from the electron-beam source passes is shaped, and a second aperture formed with an aperture in a desired transfer pattern. The electron beam passes through the second aperture and irradiates an object. The second aperture is placed on a stage, which is movable in X and Y axes directions. A registration mark is placed or positioned on at least one of the second aperture and the stage. The apparatus also includes a device such as a microscope, a charge coupled device (CCD) for observing the registration mark to position the second aperture. The observing device has variable magnifications. The second aperture can be positioned by observing the registration mark with the observing device having variable magnifications.Type: GrantFiled: November 14, 1996Date of Patent: July 21, 1998Assignee: NEC CorporationInventor: Katsuyuki Itoh
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Patent number: 5593761Abstract: An electron beam shaping mask for an electron beam with pattern writing capability, includes a substrate with various opening patterns and metallic films, which are respectively formed on top- and bottom-surfaces of the substrate. The metallic films serve as foundation metallic layers. According to the structure, a total thickness of the metallic layer is divided into the two thin metallic films. Since the substrate is protected from both sides by the metallic films, its thickness can be made to be thin. Therefore, a highly accurate patterning can be easily performed, and thermal stresses can be decreased and exfoliations of the metallic films can be avoided.Type: GrantFiled: June 2, 1995Date of Patent: January 14, 1997Assignee: NEC CorporationInventors: Katsuyuki Itoh, Hiroshi Yamashita
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Patent number: 5557110Abstract: Window-like openings are cut through an aperture with cell projecting blocks using an electron beam system with pattern writing capability, and isolated patterns are supported by microbridges in respective openings. Widths of the microbridges are less than the resolution limitation of the electron beam, and thereby isolated patterns, such as frame-shaped shading patterns, can be written of a resist film, and the through-put of the lithography process can be increased. The aperture with cell projecting blocks can be formed so as to utilize both positive and negative resist film masks.Type: GrantFiled: January 19, 1995Date of Patent: September 17, 1996Assignee: NEC CorporationInventor: Katsuyuki Itoh
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Patent number: 5438207Abstract: In an electron beam direct writing system having an aperture member, an evaluation aperture is provided for the aperture member for mapping evaluation patterns in a drawn pattern on a semiconductor substrate. Short lines having a predetermined width are arranged at first pitches in horizontal and vertical directions in peripheral portions of a first shot pattern to form a first line/interval pattern. Similarly, short lines are arranged at second pitches slightly different from the first pitches in the horizontal and vertical directions in peripheral portions of second and third shot patterns to form second line/interval patterns. Quantities of rotation and gain of a shot are determined from matching positions between evaluation patterns of the shot patterns. It is permitted in a short period of time to adjust the exposure dose, correct positional errors such as a stitching error, align component members and achieve an evaluation on reproductivity.Type: GrantFiled: November 4, 1994Date of Patent: August 1, 1995Assignee: NEC CorporationInventors: Katsuyuki Itoh, Hiroshi Yamashita
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Patent number: 4545670Abstract: A developing apparatus for electrophotography is disclosed which comprises a toner hopper as a vessel of a magnetic developer, the toner hopper having an opening formed between one side plate of the toner hopper and a developing sleeve to effect delivery and recovery of the magnetic developer, the developing sleeve being rotated from a developing zone for developing a latent image on a latent image-bearing member with the magnetic developer toward the opening and the plate of said toner hopper other than the opening being in abutting contact with the surface of the developing sleeve, a magnet roll comprising a plurality of magnets, which is rotated in the same direction as the rotation direction of the developing sleeve on the inner side of the developing sleeve, and a stopper for regulating the zone of delivery of a layer of the magnetic developer on the surface of the developing sleeve by causing the top end of the stopper to abut on or come close to the surface of the developing sleeve along the directionType: GrantFiled: October 11, 1983Date of Patent: October 8, 1985Assignee: Oki Electric Industry Co., Ltd.Inventors: Katsuyuki Itoh, Shinichi Itoh, Michiaki Otsuki