Patents by Inventor Katsuyuki KITAMOTO

Katsuyuki KITAMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230301111
    Abstract: A semiconductor storage device includes a processing circuit provided on a substrate, a plurality of first electrodes connected to the processing circuit, and a plurality of second electrodes connected to the plurality of first electrodes. The semiconductor storage device also includes a memory cell array connected to the plurality of second electrodes. The memory cell array includes a block, and the block includes a string unit. Each string unit includes a plurality of memory cells, and a plurality of column-shaped parts penetrating through at least one stack body that is a stack of a plurality of electrode films between which an insulating film is interposed. The semiconductor storage device includes a slit insulating, for each string unit, a source line electrically connected to a portion of the plurality of memory cells and a source line electrically connected to another portion of the memory cells.
    Type: Application
    Filed: September 9, 2022
    Publication date: September 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Kenta YAMADA, Yosuke MITSUNO, Takuya SUZUKI, Katsuyuki KITAMOTO, Ken KOMIYA
  • Publication number: 20220310509
    Abstract: A semiconductor storage device includes a first wiring layer, a first insulating layer on the first wiring layer, a second wiring layer on the first insulating layer, a second insulating layer on the second wiring layer, a third wiring layer on the second insulating layer, and a first pillar that passes through the first, second, and third wiring layers and the first and second insulating layers along a first direction and includes a first semiconductor layer. A first distance between side surfaces of the first wiring layer and the first insulating layer facing the first pillar is greater than a second distance between side surfaces of the second wiring layer and the second insulating layer facing the first pillar and a third distance between the side surfaces of the second insulating layer and the third wiring layer facing the first pillar.
    Type: Application
    Filed: September 3, 2021
    Publication date: September 29, 2022
    Inventors: Ryota SUZUKI, Ken KOMIYA, Katsuyuki KITAMOTO
  • Patent number: 11342354
    Abstract: A semiconductor storage device includes a stacked body including conductive layers stacked in a first direction; columnar bodies of a first group extending in the first direction in the stacked body, wherein memory cell transistors are respectively formed at intersections of the conductive layers and the columnar bodies of the first group; columnar bodies of a second group that are arranged in a second direction, and respectively include an insulating material; and an insulating film extending in the first direction and the second direction in the stacked body, and divides the stacked body to include a first portion adjacent to the columnar bodies of the first group, a second portion adjacent to the columnar bodies of the second group, a third portion between the first portion and the second portion, and a first protruding part protruding from one side surface in the third direction in the third portion.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 24, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yosuke Kanno, Katsuyuki Kitamoto
  • Publication number: 20220069093
    Abstract: A semiconductor device includes: a plurality of first electrode films stacked in a state of being insulated from each other; a plurality of semiconductor members extending in a stacked direction of the plurality of first electrode films in a stacked body of the plurality of first electrode films; a plurality of charge storage members provided between the plurality of first electrode films and the plurality of semiconductor members; a first conductive film having a first surface, and commonly connected to the plurality of semiconductor members on the first surface; a first insulating film provided on a second surface of the first conductive film on the side opposite to the first surface; a contact provided in the first insulating film and connected to the first conductive film; and a second conductive film provided on the first insulating film and connected to the contact.
    Type: Application
    Filed: March 3, 2021
    Publication date: March 3, 2022
    Inventors: Masayoshi TAGAMI, Katsuyuki KITAMOTO, Ken KOMIYA
  • Patent number: 11201219
    Abstract: An integrated circuit device of an embodiment includes a substrate, a first transistor, an insulation layer, a first contact, a second contact, and a first single crystal portion. The first transistor includes a first gate electrode, and a first drain region, and wherein the first source region and the first drain region are disposed in the substrate. The first contact faces the first gate electrode. The second contact faces a first region that is first one of the first source region and the first drain region. The first single crystal portion is disposed on the first region and convex from a surface of the first region, and is located between the first region and the second contact.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: December 14, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoya Inden, Katsuyuki Kitamoto
  • Publication number: 20210167176
    Abstract: An integrated circuit device of an embodiment includes a substrate, a first transistor, an insulation layer, a first contact, a second contact, and a first single crystal portion. The first transistor includes a first gate electrode, and a first drain region, and wherein the first source region and the first drain region are disposed in the substrate. The first contact faces the first gate electrode. The second contact faces a first region that is first one of the first source region and the first drain region. The first single crystal portion is disposed on the first region and convex from a surface of the first region, and is located between the first region and the second contact.
    Type: Application
    Filed: March 12, 2019
    Publication date: June 3, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya INDEN, Katsuyuki KITAMOTO
  • Publication number: 20210091107
    Abstract: A semiconductor storage device includes a stacked body including conductive layers stacked in a first direction; columnar bodies of a first group extending in the first direction in the stacked body, wherein memory cell transistors are respectively formed at intersections of the conductive layers and the columnar bodies of the first group; columnar bodies of a second group that are arranged in a second direction, and respectively include an insulating material; and an insulating film extending in the first direction and the second direction in the stacked body, and divides the stacked body to include a first portion adjacent to the columnar bodies of the first group, a second portion adjacent to the columnar bodies of the second group, a third portion between the first portion and the second portion, and a first protruding part protruding from one side surface in the third direction in the third portion.
    Type: Application
    Filed: February 28, 2020
    Publication date: March 25, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Yosuke KANNO, Katsuyuki KITAMOTO
  • Publication number: 20180269226
    Abstract: A semiconductor memory device includes a substrate, a first stacked body provided in a first region on the substrate, a transistor formed in a second region of the substrate, and a block member provided between the first stacked body and the transistor. The first stacked body includes a plurality of first silicon oxide films and a plurality of electrode films stacked alternately one by one. Diffusion coefficient of hydrogen in the block member is lower than diffusion coefficient of hydrogen in silicon oxide.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 20, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Takeshi Sonehara, Shigehiro Yamakita, Takeshi Sakaguchi, Ken Komiya, Katsuyuki Kitamoto, Tomohiro Yamada, Ryota Fujitsuka, Nobuhito Kuge
  • Patent number: 9892930
    Abstract: A semiconductor memory device includes a first electrode layer; a second electrode layer provided above the first electrode layer; a first insulating oxide layer provided between the first and second electrode layers; a semiconductor layer extending through the first electrode layer, the first insulating oxide layer and the second electrode layer that are stacked in the first direction; and a second insulating oxide layer extending in the first direction between the semiconductor layer and the first insulating oxide layer, the second insulating oxide layer being in contact with the first insulating oxide layer. At least one of the first insulating oxide layer and the second insulating oxide layer includes nitrogen atoms. The nitrogen atoms are distributed around an interface between the first insulating oxide layer and the second insulating oxide layer, or distributed in the vicinity of the interface.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Shinji Mori, Masayuki Tanaka, Katsuyuki Kitamoto
  • Publication number: 20140070110
    Abstract: In one embodiment, an atom probe measuring apparatus includes an X-ray source configured to generate an X-ray. The apparatus further includes an optical system configured to irradiate a sample with the X-ray. The apparatus further includes a power supply configured to apply a voltage to the sample. The apparatus further includes a detector configured to detect ions evaporated from the sample by irradiating the sample with the X-ray with applying the voltage to the sample.
    Type: Application
    Filed: February 28, 2013
    Publication date: March 13, 2014
    Inventors: Katsuyuki KITAMOTO, Haruko AKUTSU