Patents by Inventor Katsuyuki Tarui

Katsuyuki Tarui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080157359
    Abstract: An electronic component according to the present invention includes a land 112 having a flat reference surface p1 and having a solder joint p3 to be solder bonded, wherein the solder joint p3 as a concave 113 recessed from the reference surface, and a nickel plate layer 114 is laminated on a surface of the land 112, and a position of an interface between (a) a tin-containing alloy layer 116 formed on the solder joint p3 of the nickel plate layer 114 in solder bonding the nickel plate layer 114 and (b) the nickel plate layer 114 deviates from a plane including the reference surface p1. This makes it possible to provide an electronic component including a solder joint which hardly cracks.
    Type: Application
    Filed: December 18, 2007
    Publication date: July 3, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masato Yokobayashi, Katsuyuki Tarui
  • Patent number: 6118184
    Abstract: A method of manufacturing a semiconductor device including two semiconductor chips having mutually different element forming face areas on respective surfaces of a die pad of a lead frame prepared by sealing the semiconductor chips with resin by setting the lead frame in a resin sealing use mold having an injection gate for injecting therethrough a sealing resin, includes the steps of: (a) mounting the semiconductor chips on respective surfaces of the die pad in such a manner that when setting the lead frame in the resin sealing use mold, a distance between a side face of the semiconductor chip having a larger element forming face area on the injection gate side and a side face of the semiconductor chip having a smaller element forming face area on the injection gate side becomes shorter than a distance when these semiconductor chips are mounted at a center on respective surfaces of the die pad; (b) setting the lead frame in the resin sealing use mold so that the above side faces of the semiconductor chips ar
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: September 12, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiya Ishio, Hiroyuki Nakanishi, Katsunobu Mori, Katsuyuki Tarui
  • Patent number: 6104084
    Abstract: An insulation material and a wire pattern are provided on at least one of the surfaces of a die pad. Wires of the wire pattern are patterned in such a manner that at least one inner lead included in at least one of two lead groups is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the lead group including the above particular inner lead, while at least one inner lead included in the other lead group is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the other lead group. Accordingly, a multichip-1-package semiconductor device using any kind of semiconductor chip can be realized. Also, the costs of the semiconductor device are saved and the semiconductor device can be developed in a shorter period by omitting the design modification of the semiconductor chip.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: August 15, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiya Ishio, Hiroyuki Nakanishi, Tomoyo Maruyama, Katsunobu Mori, Katsuyuki Tarui