Abstract: A semiconductor device may include: a drift region of a first conductivity type; a base region of a second conductivity type arranged on the drift region; an emitter region of the first conductivity type arranged on the base region; a field stop region of the first conductivity type arranged in contact with the drift region; a collector region of the second conductivity type in contact with the field stop region; a main gate electrode electrically insulated from the base region and the collector region; a control gate electrode electrically insulated from the base region and the collector region; a gate pad on the drift region; a first resistor electrically connected between the gate pad and the main gate electrode; and a second resistor electrically connected between the gate pad and the control gate electrode. A resistance value of the first resistor may be greater than the second resistor thereof.

Abstract: A semiconductor device may include: a drift region of a first conductivity type; a base region of a second conductivity type arranged on the drift region; an emitter region of the first conductivity type arranged on the base region; a field stop region of the first conductivity type arranged in contact with the drift region; a collector region of the second conductivity type in contact with the field stop region; a main gate electrode electrically insulated from the base region and the collector region; a control gate electrode electrically insulated from the base region and the collector region; a gate pad on the drift region; a first resistor electrically connected between the gate pad and the main gate electrode; and a second resistor electrically connected between the gate pad and the control gate electrode. A resistance value of the first resistor may be greater than the second resistor thereof.

Abstract: A semiconductor device includes a switching element chip, in which a switching element is formed; a first sensing element, which is provided in the switching element chip and is configured to detect first output voltage based on an operating current of the switching element; a second sensing element, which is provided outside the switching element chip and is configured to detect second output voltage based on the operating current of the switching element; and a control circuit, which detects the operating current based on the second output voltage and interrupts the switching element, based on the first output voltage of the first sensing element and the detected operating current, when the switching element is overheated.

Abstract: A semiconductor device includes: a first conductivity-type collector region; a second conductivity-type field stop region disposed on the collector region; a second conductivity-type drift region, which is disposed on the field stop region and has an impurity concentration lower than the field stop region; a first conductivity-type base region disposed on the drift region; and a second conductivity-type emitter region disposed on the base region, wherein an impurity concentration gradient in a film thickness direction of the field stop region is larger in a region adjacent to the collector region than in a region adjacent to the drift region.

Abstract: A semiconductor device includes: a first conductivity-type collector region; a second conductivity-type field stop region disposed on the collector region; a second conductivity-type drift region, which is disposed on the field stop region and has an impurity concentration lower than the field stop region; a first conductivity-type base region disposed on the drift region; and a second conductivity-type emitter region disposed on the base region, wherein an impurity concentration gradient in a film thickness direction of the field stop region is larger in a region adjacent to the collector region than in a region adjacent to the drift region.

Abstract: A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.

Abstract: A semiconductor device includes a p-type collector region, a drift region arranged on the collector region, a base region arranged on the drift region, an emitter region arranged on the base region, a gate oxide film arranged on the bottom surface and side surface of a trench which penetrates the emitter region and the base region, and a gate electrode embedded in the inside of the trench so as to be opposed to the base region while interposing the gate oxide film therebetween, wherein the position of the lower surface of the base region is shallower in the region brought into contact with the gate oxide film than in the region spaced apart from the gate oxide film.

Abstract: A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.

Abstract: A semiconductor device includes a switching element chip, in which a switching element is formed; a first sensing element, which is provided in the switching element chip and is configured to detect first output voltage based on an operating current of the switching element; a second sensing element, which is provided outside the switching element chip and is configured to detect second output voltage based on the operating current of the switching element; and a control circuit, which detects the operating current based on the second output voltage and interrupts the switching element, based on the first output voltage of the first sensing element and the detected operating current, when the switching element is overheated.

Abstract: A semiconductor device includes a p-type collector region, a drift region arranged on the collector region, a base region arranged on the drift region, an emitter region arranged on the base region, a gate oxide film arranged on the bottom surface and side surface of a trench which penetrates the emitter region and the base region, and a gate electrode embedded in the inside of the trench so as to be opposed to the base region while interposing the gate oxide film therebetween, wherein the position of the lower surface of the base region is shallower in the region brought into contact with the gate oxide film than in the region spaced apart from the gate oxide film.

Abstract: An IGBT having a good balance between high switching speed and low on-resistance. Specifically disclosed is an IGBT 10 in which a defect layer 25 is formed in an n layer 102 in an active region 20 and formed in a p-type substrate 101 in a non-active region 40. In other words, the defect layer 25 in the active region 20 is at a shallower position than the defect layer 25 in the non-active region 40 when viewed from the surface. Due to this configuration, the switching speed is increased by reducing the amount of holes injected in the non-active region 40 in the IGBT 10. Meanwhile, the reduction of hole injection amount in the active region 20 is smaller than that in the non-active region 40, and thus increase in the on-resistance is suppressed at that time.

Abstract: The present invention provides a semiconductor device and manufacturing method of the semiconductor device which can prevent breaks in an interlayer insulation film (12) and electrode (13) that arise with bonding while maintaining bonding strength. A semiconductor element (1) mounted on a semiconductor device including an interlayer insulation film (12) which has an aperture part (123) having an opening shape which is defined by an extension part (121) which covers the gate electrode (116) and extends in the first direction, a connection part (122), the extension part (121) and the connection part (122) which connects at fixed intervals in the first direction a pair of extension parts (121) which are adjacent to the second direction, and which exposes a main surface of a base region (112) and a main surface of an emitter region (113).

Abstract: Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate.

Abstract: An IGBT having a good balance between high switching speed and low on-resistance. Specifically disclosed is an IGBT 10 in which a defect layer 25 is formed in an n layer 102 in an active region 20 and formed in a p-type substrate 101 in a non-active region 40. In other words, the defect layer 25 in the active region 20 is at a shallower position than the defect layer 25 in the non-active region 40 when viewed from the surface. Due to this configuration, the switching speed is increased by reducing the amount of holes injected in the non-active region 40 in the IGBT 10. Meanwhile, the reduction of hole injection amount in the active region 20 is smaller than that in the non-active region 40, and thus increase in the on-resistance is suppressed at that time.

Abstract: A semiconductor device 10 comprises a P type base region 13 formed in an N? type base region 11, and N+ type emitter regions 14 formed plurally in the P type base region 13 so as to be spaced form each other. The N+ type emitter regions 14 are formed such that the rate of the area occupied by the N+ type emitter region 14 in the P type base region 13 at the center part of the semiconductor device 10 is smaller than the rate of the area occupied by the N+ type emitter region 14 in the P type base region 13 at the peripheral part of the semiconductor device 10.

Abstract: A semiconductor device 10 includes a first transistor 11 placed on a substrate 16, a second transistor 12 placed on the first transistor 11 via a heat radiation layer 17, a third transistor 13 placed on the substrate 16, and a fourth transistor 14 placed on the third transistor 11 via a heat radiation layer 17. The first transistor 11 has a first region corresponding to a region where the second transistor is placed, and a second region which is formed so as to surround the first region and in which the rate of area occupied by the emitter region in the base region is higher than in the first region. Likewise the first transistor 11, the third transistor 13 has a region in which the rate of area occupied by the emitter region in the base region is varied.

Abstract: A reliable semiconductor device is provided which comprises lower and upper IGBTs 1 and 2 preferably bonded to each other by solder, and a wire strongly connected to lower IGBT 1. The semiconductor device comprises a lower IGBT 1, a lower electrode layer 5 secured on lower IGBT 1, an upper electrode layer 6 secured on lower electrode layer 5, an upper IGBT 2 secured on upper electrode layer 6, and a solder layer 7 which connects upper electrode layer 6 and upper IGBT 2. Lower and upper electrode layers 5 and 6 are formed of different materials from each other, and upper electrode layer 6 has a notch 36 to partly define on an upper surface 5a of lower electrode layer 5 a bonding region 15 exposed to the outside through notch 36 so that one end of a wire 8 is connected to bonding region 15. Upper electrode layer 6 can be formed of one material superior in soldering, and also, lower electrode layer 5 can be formed of another material having a high adhesive strength to wire 8.

Abstract: The present invention provides a semiconductor device and manufacturing method of the semiconductor device which can prevent breaks in an interlayer insulation film (12) and electrode (13) that arise with bonding while maintaining bonding strength. A semiconductor element (1) mounted on a semiconductor device including an interlayer insulation film (12) which has an aperture part (123) having an opening shape which is defined by an extension part (121) which covers the gate electrode (116) and extends in the first direction, a connection part (122), the extension part (121) and the connection part (122) which connects at fixed intervals in the first direction a pair of extension parts (121) which are adjacent to the second direction, and which exposes a main surface of a base region (112) and a main surface of an emitter region (113).

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer and being in the shape of an island on the second semiconductor layer, a dielectric film on the second and third semiconductor layers, a control electrode on the dielectric film, a first main electrode electrically connected to the second and third semiconductor layers, and a second main electrode electrically connected to the first semiconductor layer and having a Pd layer.

Abstract: An IGBT is disclosed which has a set of inside trenches and an outside trench formed in its semiconductor substrate. The substrate has emitter regions adjacent the trenches, a p-type base region adjacent the emitter regions and trenches, and an n-type base region comprising a first and a second subregion contiguous to each other. The first subregion of the n-type base region is contiguous to the inside trenches whereas the second subregion, less in impurity concentration than the first, is disposed adjacent the outside trench. Breakdown is easier to occur than heretofore adjacent the inside trenches, saving the device from destruction through mitigation of a concentrated current flow adjacent the outside trench.