Abstract: A mechanism is provided for identifying a wire-pull test location on a wire of a microelectronic package. A first distance between a first terminating location of the wire on the microelectronic package and a second terminating location of the wire on the microelectronic package is determined. Based on the first distance, a second distance from either the first terminating location or the second terminating location is determined as the wire-pull test location for testing a strength of a connection of the wire to at least one of the first terminating location or the second terminating location. An adjustment is performed such that a visual guide is oriented on the wire at the wire-pull test location.

Abstract: A mechanism is provided for identifying a wire-pull test location on a wire of a microelectronic package. A first distance between a first terminating location of the wire on the microelectronic package and a second terminating location of the wire on the microelectronic package is determined. Based on the first distance, a second distance from either the first terminating location or the second terminating location is determined as the wire-pull test location for testing a strength of a connection of the wire to at least one of the first terminating location or the second terminating location. An adjustment is performed such that a visual guide is oriented on the wire at the wire-pull test location.

Abstract: A mechanism is provided for identifying a wire-pull test location on a wire of a microelectronic package. A first distance between a first terminating location of the wire on the microelectronic package and a second terminating location of the wire on the microelectronic package is determined. Based on the first distance, a second distance from either the first terminating location or the second terminating location is determined as the wire-pull test location for testing a strength of a connection of the wire to at least one of the first terminating location or the second terminating location. An adjustment is performed such that a visual guide is oriented on the wire at the wire-pull test location.

Abstract: A mechanism is provided for identifying a wire-pull test location on a wire of a microelectronic package. A first distance between a first terminating location of the wire on the microelectronic package and a second terminating location of the wire on the microelectronic package is determined. Based on the first distance, a second distance from either the first terminating location or the second terminating location is determined as the wire-pull test location for testing a strength of a connection of the wire to at least one of the first terminating location or the second terminating location. An adjustment is performed such that a visual guide is oriented on the wire at the wire-pull test location.

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.

Abstract: Embodiments of the present invention provide a semiconductor package which includes: a semiconductor chip to which one end of each of a plurality of wires is connected; and a board on which the semiconductor chip is fixed, and a plurality of board wires to which the plurality of corresponding wires are connected are disposed, wherein the board includes: a first wiring pair that includes a first pair of wires in parallel with each other and first two board wires connected to the corresponding wires, one of the wires connected to one of the board wires crossing the other board wire without contact with the other board wire, and a second wiring pair that is provided adjacent to the first wiring pair and includes a second pair of wires in parallel with each other and second two board wires connected to the corresponding wires without a crossing.

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.

Abstract: Embodiments of the present invention provide a semiconductor package which includes: a semiconductor chip to which one end of each of a plurality of wires is connected; and a board on which the semiconductor chip is fixed, and a plurality of board wires to which the plurality of corresponding wires are connected are disposed, wherein the board includes: a first wiring pair that includes a first pair of wires in parallel with each other and first two board wires connected to the corresponding wires, one of the wires connected to one of the board wires crossing the other board wire without contact with the other board wire, and a second wiring pair that is provided adjacent to the first wiring pair and includes a second pair of wires in parallel with each other and second two board wires connected to the corresponding wires without a crossing.

Abstract: A method of package-to-board impedance matching for high speed integrated circuits (ICs). Multiple solder balls are attached to an IC package. The IC package includes multiple conductive interconnect layers, where one of the conductive interconnect layers is coupled to one or more of the multiple solder balls. Multiple vias are coupled between different conductive interconnect layers. An inductive element is coupled between an interconnect lead and a via land in the conductive interconnect layer within the IC package. The physical layout dimensions of the inductive element are configured such that the inductive element provides an inductance value that is sufficient to offset a parasitic capacitance provided by the conductive interconnect layers and the solder balls. The inductive element may be a bond wire, an inductive interconnect, or a spiral interconnect.

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip in the semiconductor package. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. The central electrode pads and the conductor plate may also be connected together using gold stud bumps.

Abstract: A TAB (tape automated bonding) tape is disclosed which includes one or more openings, each adapted to receive a semiconductor chip, and electrical leads extending into each such opening. Significantly, this TAB tape also includes means for preventing a semiconductor chip, positioned within a tape opening, from being lifted toward a bonding tool as a result of electrical leads adhering to the bonding tool, when the bonding tool is used to bond contact pads on the semiconductor chip to the leads extending into the opening.

Abstract: A TAB (tape automated bonding) tape is disclosed which includes one or more openings, each adapted to receive a semiconductor chip, and electrical leads extending into each such opening. Significantly, this TAB tape also includes a device for preventing a semiconductor chip, positioned within a tape opening, from being lifted toward a bonding tool as a result of electrical leads adhering to the bonding tool, when the bonding tool is used to bond contact pads on the semiconductor chip to the leads extending into the opening.