Patents by Inventor Katuhiro Morisuye

Katuhiro Morisuye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bipolar logic circuit having two multi-emitter transistors with an emitter of one connected to the collector of the other to prevent saturation
    Patent number: 4697102
    Abstract: A logic circuit is provided which includes a first multi-emitter transistor with its emitters coupled to a group of first input lines and a first transistor with its base coupled to the collector of said first multi-emitter transistor. A second transistor is also provided with its base coupled to the collector of said first transistor, said second transistor having a polarity opposite to that of said first multi-emitter transistor. A second multi-emitter transistor is connected with its base coupled to the collector of said second transistor and with its emitters coupled to a group of second input lines, and a third transistor is connected with its base coupled to the collector of said second multi-emitter transistor and with its collector coupled to an output line. The collector of said first multi-emitter transistor is coupled to the emitter of said second multi-emitter transistor in order to absorb minority carriers stored in the transistors. This feature significantly improves the circuit operating speed.
    Type: Grant
    Filed: May 28, 1985
    Date of Patent: September 29, 1987
    Assignees: Hitachi Microcomputer Engineering Co., Ltd., Hitachi, Ltd.
    Inventors: Takahiro Okabe, Makoto Hayashi, Katuhiro Morisuye, Tomoyuki Watanabe, Katsuyoshi Washio, Setsuo Ogura, Makoto Furihata, Shizuo Kondo