Abstract: In a drive circuit for a display apparatus into which a digital video signal is input and in which a plurality of parallel signal electrodes are provided, one of signal voltages having different levels is output in accordance with the digital video signal, or two adjacent ones of said signal voltages are simultaneously output. Alternatively, one of the signal voltages is supplied to a signal electrode in one portion of one output period, and another one of the signal voltages is supplied to the signal electrode in another portion of the output period. The length ratio of the two portions of one output period is appropriately determined according to a digital video signal, whereby an arbitrary voltage corresponding to the video signal data can be applied to the pixel.

Abstract: In a drive circuit for a display apparatus into which a digital video signal is input and in which a plurality of parallel signal electrodes are provided, one of signal voltages having different levels is output in accordance with the digital video signal, or two adjacent ones of said signal voltages are simultaneously output. Alternatively, one of the signal voltages is supplied to a signal electrode in one portion of one output period, and another one of the signal voltages is supplied to the signal electrode in another portion of the output period. The length ratio of the two portions of one output period is appropriately determined according to the digital video signal, whereby an arbitrary voltage corresponding to the video signal data can be applied to the pixel.

Abstract: In a drive circuit for a display apparatus into which a digital video signal is input and in which a plurality of parallel signal electrodes are provided, one of signal voltages having different levels is output in accordance with the digital video signal, or two adjacent ones of said signal voltages are simultaneously output. Alternatively, one of the signal voltages is supplied to a signal electrode in one portion of one output period, and another one of the signal voltages is supplied to the signal electrode in another portion of the output period. The length ratio of the two portions of one output period is appropriately determined according to a digital video signal, whereby an arbitrary voltage corresponding to the video signal data can be applied to the pixel.

Abstract: In a synchronizing signal selection circuit, in response to the input of a vertical synchronizing signal extracted from a composite synchronizing signal, a control signal is generated. The control signal is in a predetermined state during a period which begins when a first predetermined time period has elapsed after the input of the vertical synchronizing signal, and which terminates when a second predetermined time period has elapsed after the input of the vertical synchronizing signal. The composite synchronizing signal is output when the control signal is in the predetermined state, and a horizontal synchronizing signal separated the composite synchronizing signal is output when the control signal is in a state other than the predetermined state.