Patents by Inventor Katura Abe

Katura Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device with plural unit regions in which one or more MOSFETs are formed
    Patent number: 6707139
    Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: March 16, 2004
    Assignees: Hitachi, Ltd., Hitachi, ULSI Systems Co., LTD
    Inventors: Isamu Fujii, Kiyoshi Nakai, Yukihide Suzuki, Sadayuki Morita, Hidekazu Egawa, Katura Abe, Noriaki Sakamoto
  • Semiconductor integrated circuit device
    Publication number: 20020030212
    Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.
    Type: Application
    Filed: August 14, 2001
    Publication date: March 14, 2002
    Inventors: Isamu Fujii, Kiyoshi Nakai, Yukihide Suzuki, Sadayuki Morita, Hidekazu Egawa, Katura Abe, Noriaki Sakamoto
  • Semiconductor integrated circuit device
    Patent number: 6274895
    Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: August 14, 2001
    Assignees: Hitachi, LTD, Hitachi ULSI Systems Co., LTD
    Inventors: Isamu Fujii, Kiyoshi Nakai, Yukihide Suzuki, Sadayuki Morita, Hidekazu Egawa, Katura Abe, Noriaki Sakamoto