Patents by Inventor Katutoshi Tamura
Katutoshi Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9530569Abstract: The present invention provides a method for manufacturing a solid electrolytic capacitor element, wherein a dielectric layer, a semiconductor layer, a carbon layer and a silver layer are sequentially formed on a tungsten base material. This method is characterized in that: the formation of the carbon layer is carried out by laminating a carbon paste on the semiconductor layer; the carbon paste is an aqueous resin solution containing carbon particles; and a repair formation treatment is carried out after the formation of the carbon layer but before the formation of the silver layer. The time duration of the repair formation treatment is 1-40 minutes; the current density is 0.05-2.5 mA/piece; and the treatment temperature is 0-40° C.Type: GrantFiled: May 23, 2013Date of Patent: December 27, 2016Assignee: SHOWA DENKO K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20150187505Abstract: The present invention provides a method for manufacturing a solid electrolytic capacitor element, wherein a dielectric layer, a semiconductor layer, a carbon layer and a silver layer are sequentially formed on a tungsten base material. This method is characterized in that: the formation of the carbon layer is carried out by laminating a carbon paste on the semiconductor layer; the carbon paste is an aqueous resin solution containing carbon particles; and a repair formation treatment is carried out after the formation of the carbon layer but before the formation of the silver layer. The time duration of the repair formation treatment is 1-40 minutes; the current density is 0.05-2.5 mA/piece; and the treatment temperature is 0-40° C.Type: ApplicationFiled: May 23, 2013Publication date: July 2, 2015Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Patent number: 8614880Abstract: A solid electrolytic capacitor in which a capacitor element having a positive electrode lead wire protruded from a front face of the capacitor element and a positive electrode lead terminal connected to the positive electrode lead wire is sealed with an exterior sealing element of synthetic resin except for a part of the positive electrode lead terminal. The positive electrode lead terminal is provided with a positive electrode base frame arranged along a lower surface of the exterior sealing element so as to correspond to the positive electrode lead wire, a raised connecting piece arranged to extend upward from an edge of the positive electrode base frame along a front end face and having an upper edge to which the positive electrode lead wire is connected, and reinforcing pieces provided at both side edges of the raised connecting piece.Type: GrantFiled: December 28, 2009Date of Patent: December 24, 2013Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Patent number: 8559163Abstract: The present invention relates to a reaction vessel for producing a capacitor element, which is used for forming a semiconductor layer by means of energization on two or more electric conductors each having formed on the surface thereof a dielectric layer simultaneously, by immersing the electric conductors into an electrolyte in the reaction vessel, the vessel comprising two or more negative electrode plates corresponding to the individual electric conductors and two or more constant current sources electrically connected to each of the negative electrode plates; production method for a group of capacitor elements using the reaction vessel and a capacitor using the capacitor element. According to the present invention, a large number of capacitors which each uses a semiconductor layer as one part electrode with a narrow appearance capacitance distribution can be obtained simultaneously.Type: GrantFiled: September 7, 2005Date of Patent: October 15, 2013Assignee: Showa Denko K. K.Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20110292573Abstract: A solid electrolytic capacitor capable of assuredly connecting a lead terminal and a lead wire while increasing a capacity of a capacitor element is provided. The present invention is directed to a solid electrolytic capacitor in which a capacitor element 1 having a positive electrode lead wire 12 protruded from a front face of the capacitor element 1 and an positive electrode lead terminal 2 connected to the positive electrode lead wire 12 is sealed with an exterior sealing element of synthetic resin except for a part of the positive electrode lead terminal 2.Type: ApplicationFiled: December 28, 2009Publication date: December 1, 2011Applicant: SHOWA DENKO K.K.Inventors: Kazumi NAITO, Katutoshi Tamura
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Patent number: 8026137Abstract: A method for producing a capacitor having a good capacitance appearance factor and a low ESR comprising, as one electrode (anode), an electric conductor having pores and having formed on the surface thereof a dielectric layer and, as the other electrode (cathode), a semiconductor layer formed on the electric conductor by energization in an electrolytic solution, the method comprising impregnating pores with a semiconductor layer-forming precursor before energization to render the concentration of semiconductor layer-forming precursor in pores higher than that of semiconductor layer-forming precursor in the electrolytic solution; a capacitor produced by the method; and an electronic circuit and an electronic device using the capacitor.Type: GrantFiled: October 19, 2004Date of Patent: September 27, 2011Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Patent number: 7819928Abstract: The present invention provides a capacitor production method where an electric conductor having a dielectric layer formed thereon is used as one electrode and a semiconductor layer is formed by energization to be the other electrode, comprising the energization performed through a constant current diode, and also provides a jig for producing capacitors, which is used for forming semiconductor layers by energization on two or more electric conductors each having formed on the surface thereof a dielectric layer, the jig comprising two or more current ejection-type constant current sources in accordance with the number of electric conductors, which current sources each has an output electrically connected in series with a connection terminal for the electric conductor. Use of the jig of the present invention, enables production of capacitors including semiconductor as one electrode with a small variation in the capacitance.Type: GrantFiled: July 9, 2004Date of Patent: October 26, 2010Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Patent number: 7609505Abstract: The present invention relates to a resin-molded chip solid electrolyte capacitor comprising a plurality of solid electrolyte capacitor elements horizontally laid in parallel with no gap on a pair of oppositely disposed end parts of a lead frame, and a fixing layer which is extending across the plurality of capacitor elements and fixing the capacitor elements with each other; and having low equivalent series resistance (ESR) and low leakage current (LC value), a production method of the same and an electronic device using the capacitor.Type: GrantFiled: August 12, 2004Date of Patent: October 27, 2009Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20090241311Abstract: The present invention provides a capacitor production method where an electric conductor having a dielectric layer formed thereon is used as one electrode and a semiconductor layer is formed by energization to be the other electrode, comprising the energization performed through a constant current diode, and also provides a jig for producing capacitors, which is used for forming semiconductor layers by energization on two or more electric conductors each having formed on the surface thereof a dielectric layer, the jig comprising two or more current ejection-type constant current sources in accordance with the number of electric conductors, which current sources each has an output electrically connected in series with a connection terminal for the electric conductor. Use of the jig of the present invention, enables production of capacitors including semiconductor as one electrode with a small variation in the capacitance.Type: ApplicationFiled: June 26, 2006Publication date: October 1, 2009Applicant: SHOWA DENKO K.K.Inventors: Kazumi NAITO, Katutoshi TAMURA
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Patent number: 7522404Abstract: The present invention relates to a solid electrolytic capacitor with low ESR obtained by stacking a dielectric layer on a surface of an anode body comprising a valve-acting metal or an electrically conducting oxide, further sequentially stacking a semiconductor layer and an electrically conducting layer on the dielectric layer to prepare a solid electrolytic capacitor element, and molding it with a jacket material, the electrically conducting layer having an electrically conducting paste layer mainly comprising an electrically conducting metal powder and resin, wherein the tap density of the electrically conducting metal powder is 4 g/cm3 or more, and an electronic circuit and an electronic device using the solid electrolytic capacitor.Type: GrantFiled: March 8, 2005Date of Patent: April 21, 2009Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20090090997Abstract: The present invention relates to a production method of solid electrolytic capacitor element, comprising a step of forming a semiconductor layer on a surface of a conductor having a dielectric oxide film thereon and having an anode lead connected thereto by conducting electrolytic oxidation-polymerization using pyrrole dimer at around room temperature, a solid electrolytic capacitor element produced by the method, solid electrolytic capacitor using the element and uses thereof. According to the invention, low-temperature polymerizability of pyrrole, which is inexpensive, can be suppressed, whereby the invention enables production of solid electrolytic capacitor elements having a semiconductor layer formed in industrially advantageous manner.Type: ApplicationFiled: June 30, 2006Publication date: April 9, 2009Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Patent number: 7423862Abstract: The invention relates to a process for producing a solid electrolytic capacitor element, comprising forming a semiconductor layer containing a conductive polymer on a conductor having a dielectric layer on its surface. By using the solid electrolytic capacitor element of the invention prepared by forming a semiconductor layer on the conductor having a dielectric layer on its surface by an electrification method after the conductor is impregnated with a dopant, a solid electrolytic capacitor having a favorable ESR value can be fabricated.Type: GrantFiled: December 20, 2005Date of Patent: September 9, 2008Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20070206344Abstract: The present invention relates to a solid electrolytic capacitor with low ESR obtained by stacking a dielectric layer on a surface of an anode body comprising a valve-acting metal or an electrically conducting oxide, further sequentially stacking a semiconductor layer and an electrically conducting layer on the dielectric layer to prepare a solid electrolytic capacitor element, and molding it with a jacket material, the electrically conducting layer having an electrically conducting paste layer mainly comprising an electrically conducting metal powder and resin, wherein the tap density of the electrically conducting metal powder is 4 g/cm3 or more, and an electronic circuit and an electronic device using the solid electrolytic capacitor.Type: ApplicationFiled: March 8, 2005Publication date: September 6, 2007Inventors: Kazumi Naito, Katutoshi Tamura
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Patent number: 7265965Abstract: The present invention provides a capacitor wherein increase in the ESR value after a high temperature loading test is mitigated. A capacitor element, comprising an electric conductor having formed on the surface thereof a dielectric layer as one electrode, and a semiconductor layer, carbon layer and electrode layer formed sequentially on the dielectric layer, which capacitor element is characterized in that the carbon layer contains a dopant; a carbon paste as a material of the capacitor element; a capacitor using the capacitor element; and an electronic circuit and an electronic device using the capacitor.Type: GrantFiled: July 6, 2005Date of Patent: September 4, 2007Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20070141745Abstract: A method for producing a capacitor having a good capacitance appearance factor and a low ESR comprising, as one electrode (anode), an electric conductor having pores and having formed on the surface thereof a dielectric layer and, as the other electrode (cathode), a semiconductor layer formed on the electric conductor by energization in an electrolytic solution, the method comprising impregnating pores with a semiconductor layer-forming precursor before energization to render the concentration of semiconductor layer-forming precursor in pores higher than that of semiconductor layer-forming precursor in the electrolytic solution; a capacitor produced by the method; and an electronic circuit and an electronic device using the capacitor.Type: ApplicationFiled: October 19, 2004Publication date: June 21, 2007Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Patent number: 7218505Abstract: A chip solid electrolyte capacitor with low ESR and small initial failure ratio comprising a plurality of solid electrolyte capacitor elements each produced by stacking a dielectric oxide film layer, a semiconductor layer and an electrically conducting layer in this order to form a cathode part on a surface of an anode substrate exclusive of the anode part at one end, the anode substrate comprising a sintered body of a valve-acting metal or an electrically conducting oxide or comprising the sintered body connected with a metal wire, which is a chip solid electrolyte capacitor obtained by horizontally laying the plurality of electrolyte capacitor elements in parallel with no space on a pair of oppositely disposed end parts of a lead frame such that the anode part or the metal wire and the cathode part come into contact with the lead frame, joining each element, and molding the entire with a resin while leaving outside the external terminal parts of the lead frame, wherein the volume ratio of one sintered bodyType: GrantFiled: March 2, 2004Date of Patent: May 15, 2007Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20070101565Abstract: The invention relates to an arrangement for introducing gas bubbles into a liquid, a device (1) for fastening a perforated aeration membrane (2) to an aerator base plate (3) as well as to an aerator base plate (3) therefor. The aerator base plate (3) has an undercut groove (4) in at least one rim region thereof, into which a locking body (7) clamping the membrane (2) in said groove (4) fits clampingly. The locking body (7) has a generally circular cross-section. The groove (4) has an at least substantially oval cross-section. The locking body (7) is designed to be generally cylindrical.Type: ApplicationFiled: July 9, 2004Publication date: May 10, 2007Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20060262488Abstract: The present invention relates to a resin-molded chip solid electrolyte capacitor comprising a plurality of solid electrolyte capacitor elements horizontally laid in parallel with no gap on a pair of oppositely disposed end parts of a lead frame, and a fixing layer which is extending across the plurality of capacitor elements and fixing the capacitor elements with each other; and having low equivalent series resistance (ESR) and low leakage current (LC value), a production method of the same and an electronic device using the capacitor.Type: ApplicationFiled: August 12, 2004Publication date: November 23, 2006Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20060158830Abstract: The invention relates to a process for producing a solid electrolytic capacitor element, comprising forming a semiconductor layer containing a conductive polymer on a conductor having a dielectric layer on its surface. By using the solid electrolytic capacitor element of the invention prepared by forming a semiconductor layer on the conductor having a dielectric layer on its surface by an electrification method after the conductor is impregnated with a dopant, a solid electrolytic capacitor having a favorable ESR value can be fabricated.Type: ApplicationFiled: December 20, 2005Publication date: July 20, 2006Inventors: Kazumi Naito, Katutoshi Tamura
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Publication number: 20060146481Abstract: A chip solid electrolyte capacitor with low ESR and small initial failure ratio comprising a plurality of solid electrolyte capacitor elements each produced by stacking a dielectric oxide film layer, a semiconductor layer and an electrically conducting layer in this order to form a cathode part on a surface of an anode substrate exclusive of the anode part at one end, the anode substrate comprising a sintered body of a valve-acting metal or an electrically conducting oxide or comprising the sintered body connected with a metal wire, which is a chip solid electrolyte capacitor obtained by horizontally laying the plurality of electrolyte capacitor elements in parallel with no space on a pair of oppositely disposed end parts of a lead frame such that the anode part or the metal wire and the cathode part come into contact with the lead frame, joining each element, and molding the entire with a resin while leaving outside the external terminal parts of the lead frame, wherein the volume ratio of one sintered bodyType: ApplicationFiled: March 2, 2004Publication date: July 6, 2006Inventors: Kazumi Naito, Katutoshi Tamura