Abstract: On a substrate (10), one or more inverter circuits for adjusting delay time are provided between an external clock input section (T1, T2) to which a clock signal CKH1 or CKH2 is externally input and a sampling signal generating circuit (shift register). Of the inverter circuits, only necessary inverter circuits are selected and connected, thereby delaying the sampling timing for a video signal. The connection between the inverter circuit and the signal path is achieved simply by changing a connection line pattern mask in accordance with the number of inverter circuits to be connected, and without changing other manufacturing processes.